JPH01261939A - Multiframe synchronizing device - Google Patents

Abstract

PURPOSE:To realize a multiframe synchronizing device with a small-scale circuit constitution by providing a correction circuit to correct the stored timing information of the corresponding basic frame of a storage circuit in the case of deciding as synchronizing step-out by a synchronization decision circuit. CONSTITUTION:A timing output circuit 52 outputs a timing signal at timing when the synchronizing signal of each basic frame is inputted based on the input timing information of the synchronizing signal of the storage circuit 51. The synchronization decition circuit 53 detects whether the synchronizing signal is inputted while synchronizing with this timing signal or not, and decides whether each basic frame is synchronized or synchronizing step-out. In the case of synchronizing step-out, the timing information of the corresponding basic frame of the basic frame of the storage circuit 51 is corrected by the correction circuit 54. Besides, when a forward protection circuit is provided, a synchronizing step-out indication signal is outputted from a synchronizing step-out indication circuit 57, and when a backward protection circuit is provided, a synchronization establishment signal is outputted from a synchronization circuit 50 after the number of times of continuous synchronization reaches a prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a multi-frame synchronization device that performs multi-frame synchronization detection and synchronization protection for signals having a multi-frame configuration.

The purpose is to realize a device that performs multiframe synchronization detection and synchronization protection independently for each basic frame with a small-scale circuit configuration.

A memory circuit that stores synchronization signal input timing information corresponding to each basic frame; a timing output circuit that outputs a timing signal at the synchronization signal input timing of each basic frame based on the input timing information of this storage circuit; A synchronization determination circuit that determines the synchronization state of each basic frame based on the signal and the timing signal of the timing output circuit, and a modification that corrects the storage timing information of the corresponding basic frame in the storage circuit when the synchronization determination circuit determines that synchronization is out of synchronization. It is composed of a circuit.

[Industrial application field]

The present invention relates to a multiframe synchronization device for detecting multiframe synchronization and protecting synchronization of a signal having a multiframe configuration.

For example, in a telephone switching network, when converting the frame format of a signal with a multi-frame structure used in a relay transmission line to another frame former used in an interface between devices in the same station, 5.
It is necessary to obtain multiframe synchronization on the original signal. Therefore, a multi-frame synchronization circuit is required, but such a multi-frame synchronization circuit needs to be realized with a small-scale circuit configuration.

[Conventional technology]

Assume that the formant of the multi-frame signal used in the relay transmission line is as shown in Fig. 4, for example, and this is applied to the interface between devices in the same station as shown in Fig. 5. The frame shall be converted to the frame format being used. The multi-frame signal in FIG. 4 consists of 3 data bits Di +
A total of 4 bits of multi-frame (MF) Pino 1-F for synchronization of D2 + D3 and l-biller 1-F constitute one basic frame BF, and 32 of these basic frame BFs collect current to form one frame CF. , and 24 consecutive frames CF constitute one multi-frame MF. Here is the basic frame BF.

~BF3. are mutually independent.

[Problem to be solved by the invention]

Multiframe synchronization of such multiframe signals must be performed independently for each basic frame BF, ~BF31, but if a multiframe synchronization circuit and a synchronization protection circuit are provided for each of basic frames BF, ~BF31, the basic Since the number of frames BF is large, the circuit scale becomes extremely large, and it is not realistic to realize this.

Therefore, an object of the present invention is to realize a device which performs multi-frame synchronization detection and synchronization protection independently for each basic frame with a small-scale circuit configuration.

[Means to solve problems]

FIG. 1 is a principle block diagram according to the present invention.

The multi-frame synchronization device according to the present invention includes, as one form, a storage circuit 51 that stores synchronization signal input timing information corresponding to each basic frame, and a synchronization signal input for each basic frame based on the input timing information of the storage circuit 51. A timing output circuit 52 that outputs a timing signal at a timing, and an input synchronization signal and a timing output circuit 5
a synchronization determination circuit 53 that determines the synchronization state of each basic frame based on the timing signal of No. 2; and a correction circuit that modifies the storage timing information of the corresponding basic frame in the storage circuit 53 when the synchronization determination circuit 53 determines that synchronization is out of synchronization. 54.

Further, there is a multiframe synchronization device according to the present invention.

As another form, a forward protection storage circuit 55 that stores the number of consecutive synchronization failures corresponding to each basic frame, and a synchronization determination circuit 5 are provided.
an out-of-sync count update circuit 56 that updates the number of consecutive out-of-sync times of the corresponding basic frame in the forward protection storage circuit 55 based on the out-of-sync determination in step 3; and a synchronizer that outputs an out-of-sync display signal when the number of consecutive out-of-sync times reaches a predetermined value. Disconnection display circuit 5
The apparatus further includes a forward protection circuit comprising: 7.

Further, there is a multiframe synchronization device according to the present invention.

Still another embodiment includes a backward protection storage circuit 58 that stores the number of consecutive synchronizations corresponding to each basic frame, and a synchronization that updates the number of consecutive synchronizations of the corresponding basic frame in the backward protection storage circuit 58 based on the synchronization determination by the synchronization determination circuit 53. The apparatus further includes a backward protection circuit comprising a number update circuit 59 and a synchronization establishment circuit (50) that outputs a synchronization establishment signal when the number of consecutive synchronizations reaches a predetermined value.

[Effect]

The timing output circuit 52 outputs a timing signal at the timing when the synchronization signal of each basic frame is input based on the input timing information of the synchronization signal stored in the storage circuit 51. The synchronization determination circuit 53 determines whether each basic frame is synchronized or out of synchronization by detecting whether a synchronization signal is input in synchronization with this timing signal. If the synchronization is out of synchronization, the correction circuit 54 corrects the timing information of the corresponding basic frame in the storage circuit 51 for that basic frame.

When a forward protection circuit is provided, when an out-of-synchronization count update circuit 56 detects an out-of-synchronization in the 1-synchronization determination circuit 53, the out-of-synchronization count update circuit 56 updates the forward protection storage circuit 55 for the basic frame causing the out-of-synchronization. The number of out-of-synchronization is updated, and when the number of consecutive out-of-synchronization reaches a predetermined value, the out-of-synchronization display circuit 57 outputs an out-of-synchronization display signal.

In addition, when a backward protection circuit is provided, the synchronization count update circuit 59, when synchronization is detected by the synchronization determination circuit 53,
The number of consecutive synchronizations in the backward protection storage circuit 58 is updated for the synchronized basic frame, and when the number of consecutive synchronizations reaches a predetermined value, the synchronization establishment circuit 50 outputs a synchronization establishment signal.

〔Example〕

The present invention will be described in detail below with reference to nine drawings.

FIG. 2 is a block diagram showing a multiframe synchronization device as an embodiment of the present invention. belongs to.

As mentioned above, this multi-frame signal consists of 32 basic frames BF.

~ Frame G consisting of BF3 Yu 241 hard (GF.

~GF2+) constitutes one multi-frame MF.

Each basic frame BF, consisting of MF bits F, ~B
The multi-frame synchronization pattern of F21 has the first bit as “O” followed by 23 “l”s”011111
1-.1'' pattern, and this first bit is the synchronization bit Fo.The position of the frame CF of this synchronization bit Fo is determined by each basic frame BF, ~BF3.
It's different for each person.

In FIG. 2, a synchronization bit position detection circuit l is provided for each basic frame BF, to BF2 . This circuit detects the frame GF position of the synchronization bit Fo in the MF synchronization pattern for each of the multi-frame (MF
) counter 11. Selector 12. Shift register 13.
and a magnitude comparator 14.

The MF counter 11 has 24
frames GF, ~GF2. This is a free-run counter that counts the number of , and designates the frame number by repeatedly counting the numbers from 1 to 24 by incrementing by 1 for each frame.

The shift register 13 has stages equal to the number of basic frames (that is, 32 stages), and each stage holds a frame number (offcent value) from the MF counter 11 corresponding to the basic frame, and this held data is used as the basic frame BF. The shift register 13 is sequentially shifted at a period of . The frame number corresponding to each basic frame held in the shift register 13 indicates the frame number in which the synchronization pin (Fo) of each basic frame is located when synchronization is established.

When synchronization is established, the selector 12 returns the output signal 5(3) of the shift register 13 to its input side,
3 is circulated within the shift register 13, and on the other hand, when synchronization is lost, M
This is a switching circuit that switches the output signal S flll from the F count II to be input to the shift register 13 . As will be described later, this control signal SO[9 is generated at the timing when the synchronization bit Fo is input when synchronization is lost, so it is selected by the selector 12 and M
Frame number signal 5 (11) input from the F counter 11 to the shift register 13 indicates the number of the frame GF in which the synchronization bit F exists when synchronization is established for the basic frame.

The comparator 14 outputs the output signal 5(1) of the MF counter 11.
This is a magnitude comparator that compares 1 with the output signal 5 (3) of the shift register 13. When the two match, it outputs the detection signal 5 (4) of "O", and when there is a mismatch, it outputs "1". ” is output. Therefore, in the synchronization established state for the basic frame consisting of the basic frame, the synchronization bit Fo of the basic frame becomes “0” at the input timing (frame position).
A level synchronization bit position detection signal 5(4) is output.

The synchronization state detection circuit 2 receives input MF pins 1-3 (5
) synchronization bit F. is at the timing position detected by the synchronization focus position detection circuit 1 for each basic frame BF, to BF2+.

This circuit detects whether it is in sync or out of sync, and is composed of a NOR gate 21 and an XOR gate 22. The MF pinot l-S f51 and the synchronization focus position detection signal 5 (4) from the synchronization focus position detection circuit 1 are input to the NOR gate 21, and in the synchronization established state, every time the synchronization pinot 0 is input, " 1” synchronization detection signal 5 (6
) is output to the rear protection circuit 3.

Detection signal 5 (4) and MF bit 5 (5) are also input to X, OR data 1-22, and this XOR gate 2
2 is the synchronization pin 1 - position detection circuit 1 when the synchronization is out of state.
Sync bit F at the sync bit position detected at . When the synchronization bit Fo is not input or when the synchronization bit Fo is input at a position other than the synchronization focus position, an out-of-synchronization detection signal 300) of the "1" level is output.

The rear protection circuit 3 is a circuit that performs three stages of rear protection, and integrates the number of consecutive MF synchronization detections and selects the specified stage (here, 3 stages).
stage), it outputs a synchronization establishment signal 5 (9) and also outputs a reset signal 3041 to the forward protection circuit 4. This backward protection circuit 3 includes an adder 31. Shift register 32. It is configured to include an AND gate 33.

The shift register 32 has the number of stages equal to the number of basic frames (that is, 32 stages), and each stage stores the number of consecutive synchronization detections in the basic frame corresponding to the basic frame as data, and the held data is stored at the cycle of the basic frame. shift. The adder 31 receives the synchronization detection signal 5 from the NOR gate 21.
(6) and the synchronization count signal 5(8) of the shift register 32 to accumulate the number of consecutive synchronization detections, and inputs the accumulated count signal 5(7) to the shift register 32. This adder 31 outputs a synchronization establishment signal 5 (which goes to "1" level) when the number of acquisitions of synchronization detection reaches 3 or more of the specified stages.
9) is output.

On the other hand, when synchronization is lost, the integrated value is reset by a reset signal 505) from the forward protection circuit 4.

A synchronization establishment signal 5 (9) and a synchronization detection signal 5 (6) are input to the AND gate 33, and the AND output thereof is output to the forward protection circuit 4 as a reset signal 5O41.

The forward protection circuit 4 is a circuit that performs three stages of forward protection, and integrates the number of consecutive out-of-synchronizations, and when the number of consecutive out-of-synchronizations reaches three or more stages, outputs an out-of-synchronization signal 5Q31 indicating an out-of-synchronization state, and also performs backward protection. A reset signal 505) is output to the adder 31 of the circuit 3.

This forward protection circuit 4 includes an adder 41. shift register 42
, AND gate 43. It is configured to include a gate 44.

The shift register 42 has the number of stages equal to the number of basic frames (that is, 32 stages), and in each stage, the number of consecutive out-of-sync detections in that basic frame is held as data corresponding to the basic frame, and the held data is stored at the cycle of the basic frame. shift. The adder 41 is a circuit that adds the out-of-synchronization detection signal SQI from the XOR gate 22 and the out-of-synchronization count signal 5021 of the shift register 42 to accumulate the number of consecutive out-of-sync detections.

The integration number signal SOυ is input to the shift register 42. This adder 41 outputs an out-of-sync signal SO of "1" level when the cumulative number of out-of-sync detections reaches three or more specified stages.
On the other hand, when waiting for synchronization establishment, the integrated value is always reset by the reset signal 5Q41 from the rear protection circuit 3.

The out-of-sync detection signal 500) and the out-of-sync signal S (l are input to the AND gate 43, and the AND output is input to the rear protection circuit 4 as a reset signal 5Q51. Inverting input terminal.

The other is an inverting input terminal, and 3 non-inverting input terminals have an out-of-synchronization signal S01, and 1 inverting input terminal has MF bit 5.
(5) is input, and its AND output is the control signal S
It is output as al to the selector 12 of the synchronous bit position detection circuit l. As a result, the gate 44 detects the synchronization bit Fo in the MF bit 5 (5) when synchronization is lost, generates the control signal S00, and operates to switch the selector 12.

The operation of the apparatus of this embodiment will be explained below with reference to FIG. FIG. 3 shows the state of change of each signal for a plurality of multi-frames MF1 to MF1, focusing on the basic frame BFn.

Here, from a state where multi-frame MF and MF2 were out of synchronization, multi-frame MF3 to MF? The following explanation assumes that synchronization was achieved at MF8, and synchronization was lost again after multiframe MF8.

First, the synchronization bit position detection circuit is
It operates to indicate the timing position at which the synchronization bit Fo of Fn is input. Namely.

When the MF counter 11 outputs the position of the frame GFk with the synchronization bit Fo of the basic frame BFn, the basic frame B' is output from the soft register 13.
When the frame number GFk of Fn and the frame number GFk of the MF counter 11 match, the comparator 14 outputs “0”.
A synchronization bit detection signal 5(4) is output.

At the output timing of this synchronization bit detection signal 5 (4), M
When synchronous pin 1-Fo (i.e. “'O” bit) appears in F pino l-S (51, NOR gate 2I
detects this and outputs a synchronization detection signal 5 (6) of "1" (at the position of multi-frame MF3 in FIG. 3).

This synchronization detection signal 5 (6) is sent to the adder 3 of the backward protection circuit 3.
1 and is added to the synchronization detection count value of the basic frame BFn, which is held in the shift register 32, and the added value is sent back to the shift register 32 as the cumulative count 5 (7) corresponding to the basic frame BFn. Stored. When this operation is repeated three times for multi-frames MF3 to MF5, the cumulative number of times 5 (7) of the adder 31 becomes "3", which is the specified number of protection stages, and it is determined that synchronization has been established, and the synchronization is established as "1". Signal 5 (9) is output. In this synchronization established state, the AND gate 33 sends a reset signal 5Q4) to the forward protection circuit 4 in response to the synchronization detection signal 5 (6) to reset the adder 41, so the out-of-sync signal Sα is sent from the forward protection circuit 4. is never output.

Next, because synchronization occurred in multi-frame MF8, MF bit 5 (5
) has become “1”. As a result, the output signal of the NOR gate 21 becomes "0".

On the other hand, the XOR gate 22 outputs an out-of-synchronization detection signal SQI of "1". This out-of-synchronization detection signal S(I[
I+ is input to the adder 41 and added to the out-of-synchronization count SQ21 of the basic frame BFn from the shift register 42, and the resulting cumulative count SOυ is stored in the shift register 42 again. When this operation continues for "3" times, which is the specified number of protection stages of the forward protection circuit 4, the cumulative number 800 of the adder 41 becomes "3", thereby "1".
” out-of-synchronization signal 0 is generated. This causes AND
Thereafter, the gate 43 sends out a reset signal SQ9 to the backward protection circuit 3 in response to the out-of-synchronization detection signal SQI, and the adder 3
1 is reset, so the synchronization establishment signal 5 (8) is “0”
becomes.

In this out-of-synchronization condition, gate 44 outputs the synchronization bit in the MF bit. is detected and the control signal 5Qle is activated accordingly.
is generated, the selector 12 is switched to the MF counter 11 side, and the frame number at that point is set to the basic frame BF.
Shift register 13 as frame number data corresponding to n
Store in. Under normal conditions, this frame number coincides with the frame timing at which the synchronous pin I-F o is input in the next multi-frame, so the synchronous pin I-F is input in the second multi-frame.

If it is input normally, multiframe synchronization can be achieved again.

The operation explained above is the shift register 13.32°4
By sequentially shifting the retained data of 3 in the period of the basic frame, each basic frame BF.

This is performed for each of ~BF3.

Various modifications are possible in implementing the invention. For example, the number of protection stages of the rear protection circuit and the front protection circuit is not limited to that of the embodiment, and can be independently set to any number of stages by changing the dark value of the overflow of the adder. Further, the number of basic frames constituting one frame is not limited to the embodiment, and can be applied to multi-frames of various frame formats by changing the number of stages of the shift register.

Furthermore, in the above embodiment, a shift register is used as a circuit for holding the data of each basic frame, but the circuit is not limited to this. It is also possible to configure the circuit to sequentially and cyclically read the stored data.

〔Effect of the invention〕

According to the present invention, it is possible to realize a device that performs synchronization and synchronization protection in units of mutually independent basic frames while significantly reducing the scale of one circuit.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram according to the present invention. FIG. 2 is a block diagram of a multiframe synchronization device as an embodiment of the present invention. FIG. 3 is a diagram showing changing states of signals of each part to explain the operation of the embodiment device. FIG. 4 is a diagram showing an example of a frame format of a signal having a multi-frame structure. FIG. 5 is a diagram showing a signal frame format when the signal in the format of FIG. 4 is converted. In fig. 1-Synchronization binocular position detection circuit 2-Synchronization state detection circuit 3-Backward protection circuit 4-=Forward protection circuit 11-Multi-frame counter 12-Selector 13, 32.42-Shift register 14-Magnitude comparator 31, 41-Adder 21-N OR gate 22--X OR gate [F] 5(to) 1 1 0
0S(11) 1 2
3 3S(12) 0
1 2 3S (13) OO1j S (14) ○ ○ o
. 5 (15) OOOO Actual flow Q11 No. ○ 001111 Operation explanatory diagram 3

Claims (1)

[Claims] 1. A memory circuit (51) that stores synchronization signal input timing information corresponding to each basic frame;
a timing output circuit (52) that outputs a timing signal at the synchronization signal input timing of each basic frame based on the input timing information of the timing output circuit (52); a synchronization determination circuit (53) that determines the synchronization state of
and a correction circuit (54) for correcting the storage timing information of the corresponding basic frame in the storage circuit (53) when the synchronization determination circuit (53) determines that the synchronization is out of synchronization. 2. A forward protection storage circuit (55) that stores the number of consecutive out-of-synchronizations corresponding to each basic frame; and a forward protection storage circuit (55) that stores the number of consecutive out-of-synchronizations corresponding to each basic frame; A forward protection circuit comprising an out-of-sync count update circuit (56) that updates the out-of-sync count, and an out-of-sync display circuit (57) that outputs an out-of-sync display signal when the consecutive out-of-sync count reaches a predetermined value. The multi-frame synchronization device according to claim 1, further comprising:. 3. A backward protection storage circuit (58) that stores the number of consecutive synchronizations corresponding to each basic frame; and a backward protection storage circuit (58) that stores the number of consecutive synchronizations of the corresponding basic frame in the backward protection storage circuit (58) based on the synchronization determination by the synchronization determination circuit (53). Claim 1 further comprising a backward protection circuit comprising: a synchronization number update circuit (59) for updating the number of consecutive synchronizations; and a synchronization establishment circuit (50) for outputting a synchronization establishment signal when the number of consecutive synchronizations reaches a predetermined value. Or the multi-frame synchronization device according to 2.