JP2003188844A - Phase adjustment circuit and phase adjustment method adopted by the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase adjustment circuit capable of completing phase adjustment at a high-speed to restart reading of data. <P>SOLUTION: An SDH termination processing section 1 detects a head of a frame from received data to detect a head of a multiplexed VC (Virtual Container)-3. An MFI (Multi Frame Indicator) detection section 2 detects an MFI value from an H4 byte at a fixed position on the basis of the head information. An MFI synchronous management section 3 manages the synchronous state as to the detected MFI value. A phase adjustment section 4 detects a reference VC-3 on the basis of the detected MFI value. A re-phase adjustment section 8 manages the MFI value of the VC-3 stored in a phase adjustment memory 6 and again tries to make phase adjustment by an MFI out of synchronism alarm informed from the MFI synchronous management section 3. A write control section 5 writes data to the phase adjustment memory 6 on the basis of the reference VC-3 and a read control section 9 reads data from the phase adjustment memory 6 depending on the result of write by the write control section 5. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting circuit and a phase adjusting method used for the same, and more particularly to a plurality of VCs (Vi
In a signal in which the real contour-3 is multiplexed, a virtual concatenation (Virtual Conc) composed of a plurality of VC-3 channels is used.
At the same time, the disconnection of a certain passing line or MFI (Multi Frame Indicator)
r) It relates to the phase adjustment when the MFI is out of synchronization due to a bit error in the value.

[0002]

2. Description of the Related Art STM (Synchronous Transfer) in which the above VC-3 is 48-channel multiplexed.
The frame format of Mode) -48 is shown in FIG. The STM-48 frame is composed of a section overhead 110 for transferring supervisory control data, an area 111 for storing pointer information indicating the head of the multiplexed VC-3, and a payload 114.

The payload 114 has a VC-3 (112
-1 to 112-48) are multiplexed on 48 channels, and each VC is
-3 (112-1 to 112-48) is provided with a path overhead 115 for transferring data of the supervisory control system.

A plurality of VC-3s (112-1 to 112-4)
8) is secured as one data transfer area, the virtual concatenation is ITU-T (In
international Telecommunica
region Union-Telecommunicat
Ion Standardization Secto
G. r. 707 / G. 783 standardized.

For example, two VC-3s are treated as virtual concatenation, and the node 21 in FIG.
From node to node 26. Each VC-3 may be transferred using the route 201 and the route 202. At that time, the nodes 22, 23, 2 passing through
Due to the in-apparatus delay of 4 and the delay due to the path length difference, a phase difference occurs in the node 26 receiving each VC-3. Therefore, a mechanism for absorbing this phase difference is required at the end of the virtual concatenation.

In the virtual concatenation, as a mechanism for detecting and processing the above phase difference, the H4 byte of the path overhead of each VC-3 shown in FIG. 15 has a number indicating the order relation of each VC-3. MFI (Mu
lti Frame Indicator).

[0007] Referring to FIG.
The phase difference in the case of mapping and transfer to the above will be described. When a data string is transferred using VC-3 # 1 and VC-3 # 2, the first byte of VC-3 # 1 is set to V
The second byte is alternately mapped to C-3 # 2, and so on.

Regarding the MFI value indicating the order relation, the same SDH (Synchronous Digital H
The same MFI value is assigned to VC-3 of the ierarchy frame. MFI value is SDH
It increases by 1 for each frame and returns to 0 at 4095 (maximum value of 12-bit MFI).

Since these VC-3s may be transferred by using a different route in the SDH network, the VC- in the SDH frame may be transferred to the node 26 at the node 26 due to a delay in the middle.
3 may have different MFI values. In FIG. 16, the same S
The figure shows the case where MFIs of 0 and 4095 (maximum value) exist in the DH frame.

In this example, VC-3 # 1 and VC-3
There is a phase difference of 1 frame from # 2.
Even if one byte of data is retrieved from each VC-3 and restored in this state, it cannot be restored to the original data string. Therefore, as shown in FIG. 17, it is necessary to use a memory or the like to wait for a phase early (VC-3 # 1) and restore the data string after the phases are aligned.

When performing data transmission using virtual concatenation, a mechanism for performing phase adjustment is required on the side of restoring a data string. The VC-3 that constitutes the virtual concatenation may use a separate route in the SDH network.

For example, the routes 201 and 20 in FIG.
When 2 is used, the path is switched due to the disconnection of the link between the node 22 and the node 23, the device failure of the node 22, or the like, and the continuity of the MFI value is lost (MFI
Out of sync). In this case, if the processing is continued as it is, normal data cannot be restored, so that the phase is V
It is necessary to detect C-3 and adjust the phase again.

Regarding the method of adjusting the phase when the continuity of the MFI values is lost, VC-3 # 1 to VC-3 # 3
A case where virtual concatenation is configured by will be described as an example. If the continuity of the MFI value of VC-3 # 2 is lost, the MFI value of VC-3 # 2 is detected. Detected MFI value and VC-3 # 1 and VC
-3 The VC arriving earliest from the MFI value of # 3
-3 is determined.

The detected MFI value is VC-3 # 1, V
If C-3 # 2 and VC-3 # 3 are “3”, “2”, and “5”, respectively, VC-3 # 3
Has arrived the earliest, and for VC-3 # 3, writing to the phase adjustment memory is started. With respect to the remaining VC-3 # 1 and VC-3 # 2, the reception of the MFI value “5” is detected. VC-3 # 1, VC-3
When the MFI value "5" is received in each of # 2, reading from the phase adjustment memory is started.

[0015]

However, in the above-described conventional phase adjusting method, even when the continuity of the MFI value of VC-3 # 2 is lost, VC-3 # 1, VC-
3 # 3 receives the data having the normal MFI value, and the VC-3 # 3 is used without using the MFI value.
Since the phase adjustment is performed using the MFI value detected again in 2, there is a problem that the continuity of the MFI value is lost and a delay occurs until the phase adjustment is completed when the phase adjustment is performed again.

Therefore, an object of the present invention is to solve the above problems and provide a phase adjusting circuit and a phase adjusting method used therefor capable of completing phase adjustment at high speed and resuming data reading. .

[0017]

The phase adjustment circuit according to the present invention arranges the temporal arrangement of a plurality of virtual containers in input data such that one band is provided by a plurality of virtual containers by virtual concatenation. MFI (Multi for managing
A phase adjustment circuit that performs a phase adjustment when the continuity of the Frame Indicator values is lost.
A means for writing to the phase adjustment memory about a normal virtual container in which an I-sync alarm is not detected, a means for managing the MFI value of the data written in the phase adjustment memory, and a re-detected MFI value and management MF doing
Means for performing phase adjustment using the I value. It has and.

In the phase adjusting method according to the present invention, in the input data such that one band is provided by a plurality of virtual containers by virtual concatenation, MFI (for managing the temporal arrangement of the plurality of virtual containers) is managed. Multi Frame I
(ndicator) is a phase adjustment method for performing phase adjustment when the continuity of values is lost, wherein a normal virtual container in which an MFI synchronization alarm is not detected is written in the phase adjustment memory and is written in the phase adjustment memory. The MFI value of the collected data is managed, and the phase is adjusted using the redetected MFI value and the managed MFI value.

That is, the phase adjusting circuit of the present invention is a virtual concatenation.
multiple VCs (Virtu)
alContainer) -3 or VC-4, in input data that provides one band, M in a VC-3 that constitutes virtual concatenation
FI (Multi Frame Indicator)
The feature is that the phase adjustment is performed at high speed when the continuity of the values is lost (out of MFI synchronization).

More specifically, the phase adjusting circuit according to the present invention is a V which constitutes a virtual concatenation.
MFI (Mul for managing time sequence of C-3
to detect the beginning of the frame from the received data to detect the tiFrame Indicator) information,
SDH (Synchronous Digital H) for detecting the beginning of the multiplexed VC-3 from the pointer information
erarchy) termination processing unit and multiplexed VC-3
Based on the detected MFI value, the MFI detection unit that detects the MFI value from the H4 byte at a fixed position from the head information of the MFI, the MFI synchronization management unit that determines the continuity of the MFI value and manages the MFI synchronization. A phase adjustment unit that detects the reference VC-3 in the VC-3 that constitutes the virtual concatenation, a write control unit that writes to the phase adjustment memory based on the reference VC-3, and an MFI that determines the reference VC-3.
A read control unit for reading from the phase adjustment memory when the writing of the VC-3 having the same MFI value as that of the VC-3 is completed in all the VC-3s forming the virtual concatenation, and for each multiplexed VC-3. An address management unit that manages the start address and the final address of the phase adjustment memory divided into areas, and an MFI synchronization that is notified from the MFI synchronization management unit that manages the VC-3 MFI value stored in the phase adjustment memory And a re-phase adjusting unit for performing the phase adjustment again according to the disengagement alarm.

In the above structure, the SDH termination processing section detects the frame start position of the received data, detects the pointer indicating the start position of the multiplexed VC-3 from the frame start position information, and detects the multiplexed VC- The top of 3 is detected.

The MFI detector detects the MFI value stored in the H4 byte at a fixed position from the beginning of the detected VC-3. The MFI synchronization management unit manages the synchronization state of the MFI value detected by the MFI detection unit. The phase adjuster is used for all Vs that make up the virtual concatenation.
When synchronization is established for the C-3 in the MFI synchronization management unit, the VC-3 (reference VC-
3) is determined.

The write control unit controls the reference V in the phase adjustment unit.
When C-3 is determined, writing from the reference VC-3 to the phase adjustment memory is started. With respect to the other VC-3s forming the virtual concatenation, writing is started each time a VC-3 having the same MFI value as the MFI value for which the reference VC-3 is determined is received. V with the above MFI value
When the writing of C-3 is completed for all the VC-3s forming the virtual concatenation, the read control unit is notified of the read permission signal and the reading is started.

The address management unit manages the start address and the end address of the area provided for each multiplexed VC-3. The re-phase adjustment unit receives the MFI value information of VC-3 written in the phase adjustment memory and the MFI value information of VC-3 read from the phase adjustment memory from the write control unit and the read control unit, and performs the phase adjustment. V stored in memory
It manages the MFI value of C-3.

Further, the re-phase adjusting unit detects the loss of MFI synchronization from the MFI synchronization management unit and the VC-3 in which the synchronization loss occurs.
After receiving the information, the phase adjustment is performed again for the corresponding virtual concatenation based on the managed MFI value.

The re-phase adjusting unit manages the MFI value of the VC-3 stored in the phase adjusting memory, and thereby VC-constitutes virtual concatenation.
When an MFI synchronization alarm is generated in 3, the phase adjustment is performed using the MFI value of VC-3 stored in the phase adjustment memory and the MFI value re-detected by VC-3 in which the synchronization loss occurs. This makes it possible to perform high-speed phase adjustment. That is, in the virtual concatenation composed of a plurality of VC-3 channels in a signal in which a plurality of VC-3s are multiplexed, when the MFI is out of synchronization due to a disconnection of a certain passing line or a bit error of the MFI value, etc. It is possible to perform the phase adjustment immediately and recover.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to an embodiment of the present invention. In FIG. 1, a phase adjusting circuit according to an embodiment of the present invention is an SDH.
(Synchronous Digital Hier
archy) termination processing unit 1 and MFI (Multi F)
(frameIndicator) detection unit 2, MFI synchronization management unit 3, phase adjustment unit 4, write control unit 5, phase adjustment memory 6, address management unit 7, and rephase adjustment unit 8
And a read control unit 9.

The SDH termination processing unit 1 uses a virtual concatenation (Virtual Concatenation).
on), which is a VC (Virtual Contai)
in order to detect the MFI information for managing the temporal alignment of (ner) -3, the start position of the frame is detected from the received data, and the start position of the multiplexed VC-3 is indicated from the frame start position information. The pointer is detected, and the head of the multiplexed VC-3 is detected from the pointer information.

The MFI detector 2 detects the MFI value from the H4 byte at a fixed position based on the multiplexed VC-3 head information. The MFI synchronization management unit 3 determines the continuity of the MFI values and manages the MFI synchronization, that is, manages the synchronization state of the MFI values detected by the MFI detection unit 2.

The phase adjusting section 4 detects the reference VC-3 in the VC-3 forming the virtual concatenation based on the detected MFI value. In other words, the phase adjustment unit 4 makes all the VCs forming the virtual concatenation
-3, the VC-3 that arrives earliest when the synchronization is established in the MFI synchronization management unit 3 (reference VC-
3) is determined.

The write controller 5 writes to the phase adjustment memory 6 based on the reference VC-3. That is, the write control unit 5
When the reference VC-3 is determined by the phase adjustment unit 4,
Writing from the reference VC-3 to the phase adjustment memory 6 is started. Other VCs that make up virtual concatenation
With respect to -3, writing is started each time a VC-3 having the same MFI value as the reference VC-3 is determined is received. Writing of the VC-3 having the above MFI value causes all VC-s constituting the virtual concatenation to be written.
When the process is completed for 3, the read control unit 9 is notified of the read permission signal and the reading is started.

The read control unit 9 writes all VC-3s in which the writing of the VC-3 having the same MFI value as the reference VC-3 determines the virtual concatenation.
When the process is completed in, the reading from the phase adjustment memory 6 is performed. The address management unit 7 manages the start address and the final address of the phase adjustment memory 6 divided into the multiplexed areas for each VC-3.

The re-phase adjusting unit 8 manages the MFI value of the VC-3 stored in the phase adjusting memory 6 and performs the phase adjustment again according to the MFI out-of-sync alarm notified from the MFI synchronization managing unit 3. That is, the re-phase adjustment unit 8 receives the VC-3 MFI value information written in the phase adjustment memory 6 from the write control unit 5, and reads the VC-3 MFI value information read from the phase adjustment memory 6. M of VC-3 received from the control unit 9 and stored in the phase adjustment memory 6
Manages the FI value. Further, the re-phase adjusting unit 8 receives the MFI out-of-sync and the VC-3 information in which the out-of-sync has occurred from the MFI synchronization management unit 3 and again based on the managed MFI value for the corresponding virtual concatenation. Adjust the phase.

The re-phase adjusting unit 8 manages the MFI value of the VC-3 stored in the phase adjusting memory 6 so that V which constitutes the virtual concatenation is controlled.
When the MFI synchronization alarm is generated in C-3, the phase adjustment is performed using the MFI value of VC-3 stored in the phase adjustment memory 6 and the MFI value re-detected in VC-3 in which the synchronization loss occurs. By doing so, high-speed phase adjustment can be performed.

FIG. 2 is a block diagram showing the configuration of the rephase adjusting unit 8 of FIG. In FIG. 2, the rephase adjusting unit 8 includes a reception MFI determination processing unit 81, a write completion flag update processing unit 82, a write MFI value management memory 83, and a write MF.
The I-value update processing unit 84 is included.

When the MFI value of the VC-3 in which the MFI out-of-sync alarm is generated is detected again, the reception MFI determination processing unit 81 determines the MFI value and the MFI value managed in the write MFI value management memory 83. By
The reference VC-3 is determined again for the virtual concatenation in which the out-of-sync alarm is generated.

The write MFI value update processor 84 and the write / read MFI value notified from the write controller 5 and the read controller 9 and the VC-3 in which the out-of-sync alarm occurs.
The MFI value information stored in the phase adjustment memory 6 is updated from the information and the MFI value detected again. The write completion flag update processing unit 82 manages whether or not data is stored in the phase adjustment memory 6.

FIG. 3 shows an STM (Synchronous Transfer) in the phase adjustment memory 6 shown in FIG.
FIG. 4 is a diagram showing a configuration for processing data in which VC-3 is multiplexed in Mode) -48, and FIG. 4 is a diagram showing a configuration of the write MFI value management memory 83 shown in FIG.

FIG. 5 is a diagram showing an example of bits indicating the validity / invalidity of the write MFI value management memory 83 shown in FIG. 2, and FIG. 6 is a flow chart showing the operation of the phase adjustment circuit according to one embodiment of the present invention. is there. The operation of the phase adjusting circuit according to the embodiment of the present invention will be described with reference to FIGS.

The SDH termination processing unit 1 detects the frame head position of the received data, detects the pointer indicating the head position of the multiplexed VC-3 from the frame head position information,
The head of the multiplexed VC-3 is detected.

The MFI detector 2 detects the MFI value from the H4 byte at a fixed position from the beginning of the VC-3. MF
The I value is stored in an 8-bit H4 byte as shown in FIG. H4 byte bit5 to bit8 (M
FI1) increases in SDH frame units, and
Make a round in the frame.

(Bit5, bit6, bit7, bit
8) = (0,0,0,0), bit1 of MFI2
bit4 is stored in bit1 to bit4 of H4 byte, and (bit5, bit6, bit7, bit8)
= (0,0,0,1), bit5 to bi of MFI2
t8 is stored in bit1 to bit4 of H4 byte.

An MFI value (12 bits) is composed of MFI1 (4 bits) and MFI2 (8 bits). The detected MFI value enters the MFI synchronization state when the continuity is confirmed in the reception of n times (the number of protection stages is n stages).

In all VC-3s forming the virtual concatenation, when the MFI synchronization state is established, the V which arrives earliest in the phase adjusting unit 4 is reached.
C-3 (reference VC-3) and the MFI value at that time are determined. When the reference VC-3 is determined, the write control unit 5 starts writing from the reference VC-3 to the phase adjustment memory 6.

The write controller 5 constructing a virtual concatenation other than the reference VC-3 writes to the phase adjustment memory 6 when the VC-3 having the above determined MFI value is received. To start sequentially. When writing to the phase adjustment memory 6, the final address managed by the address management unit 7 is updated, and the write MF managed by the re-phase adjustment unit 8 is updated.
Update the I value.

The write control unit 5 reads out all the VC-3s forming the virtual concatenation when the writing to the phase adjustment memory 6 is completed.
Notify the read permission to. Upon receiving the read permission, the read control unit 9 starts reading from the phase adjustment memory 6.
When reading from the phase adjustment memory 6, the start address managed by the address management unit 7 is updated, and the write MFI value managed by the rephase adjustment unit 8 is updated.

FIG. 3 shows a configuration example of the phase adjustment memory 6 in the case of processing data in which VC-3 is multiplexed in STM-48. The phase adjustment memory 6 is VC-3 # 1 to VC-3.
The area is divided into 48 areas # 48, and the area for each VC-3 is secured in SDH frame units. MFI value is 0
The maximum number of frames that can be stored is 4 because it is up to 4095.
It is a divisor of 096. For example, when a buffer for 64 frames is provided, writing is started, and when data of 65 frames or more is received in a situation where the reading control unit 9 does not start reading, the data is sequentially overwritten.

Write MFI managed by the rephase adjusting unit 8
As shown in FIG. 4, the value management memory manages a bit indicating valid / invalid for each VC-3, a head MFI value, and a final MFI value. When the first write occurs, first the valid / invalid bit is validated to set the start MFI value and the final MFI value to the MFI value at which the write occurred.
When the next write occurs, the final MFI value is updated. In the situation where the above overwrite occurs, the top MF
Both the I value and the final MFI value will be updated.

When the MFI synchronization management unit 3 detects an MFI out-of-sync alarm while the phase adjustment is completed and the reading is normally performed (step S1 in FIG. 6).
The reading of the virtual concatenation to which the corresponding VC-3 belongs is stopped (step S2 in FIG. 6). However, with respect to the normal VC-3, the writing is continued as in the normal case.

Further, the VC-3 information in which the alarm has occurred is notified to the write MFI value update processing section 84, and the corresponding V
About C-3 Write MFI value management memory 83 valid /
The invalid bit is invalidated, and the write completion flags of all virtual concatenations to which the alarmed VC-3 belongs are set to "0" (step S3 in FIG. 6). After that, the write MFI value update processing unit 84 receives the write MFI value and the read MFI value and updates the write MFI value management memory 83.

In VC-3 where an alarm is detected,
When the MFI synchronization is established again (step S4 in FIG. 6), the detected MFI value is the received MFI determination processing unit 8
1 is notified and a timer (not shown) is started (FIG. 6).
Steps S5 and S6).

In the reception MFI determination processing section 81, two processes operate in parallel. In the first process, the VC-3 in which the alarm is detected is re-detected in the MFI value, and another normal VC that constitutes the virtual concatenation is formed.
-3 is a process of reading the head MFI value of -3 from the MFI value management memory 83 and performing comparison (step S7 to FIG.
S9). Since all the head MFI values after the phase adjustment are the same, VC- that constitutes the virtual concatenation
You can select any of the three normal ones.

The second process is V when an alarm is detected.
This is a process of holding the MFI value detected again in C-3 and determining whether or not the data of the MFI value is written in the phase adjustment memory 6 in another normal VC-3 (step in FIG. 6). S7, S8, S12). When the MFI value data is written in the phase adjustment memory 6, the write completion flag update processing unit 82 is notified. The write completion flag update processing unit 82 updates the write completion flag, and at the same time, the VC-3 having the MFI value detected again.
Is completed for all the VC-3s forming the virtual concatenation by judging whether the write completion flag is set to "1".

These two processes do not satisfy the condition at the same time, and if they satisfy the condition, either one of them is performed. Further, if neither condition satisfies the condition within a certain period of time (step S8 in FIG. 6), it means that the phase difference in the range in which the phase adjustment can be performed in the phase adjustment memory 6 is exceeded. A phase adjustment alarm indicating that adjustment is impossible is issued (step S15 in FIG. 6).

When the condition is satisfied in the former process, the VC-in which the alarm is generated in the write MFI value management memory 83
3 to update the start MFI value of the normal VC-3 to the start MFI value of a normal VC-3, and set the start address managed by the address management unit 7 to VC- which constitutes the virtual concatenation including the VC-3 in which the alarm is generated. About MF
Update to the head address where the VC-3 having the I value is stored. Then, the timer is stopped (step S1 in FIG. 6).
0), the reading of the phase adjustment memory 6 is started from the area in which the head MFI value is stored (step S11 in FIG. 6).

When the condition is satisfied in the latter process, the head MFI value of the VC-3 forming the virtual concatenation including the VC-3 in which the alarm is generated is set to the MFI value detected again after the alarm is generated. The VC-3 having the MFI value re-detected after the alarm is generated is updated for the VC-3 constituting the virtual concatenation including the VC-3 in which the alarm has occurred by updating the start address managed by the address management unit 7. Update to the first address stored. Then, the timer is stopped (step S13 in FIG. 6), and the reading of the phase adjustment memory 6 is started from the area in which the MFI value detected again after the alarm is generated is stored (step S14 in FIG. 6).

FIG. 7 shows a VC-3 according to an embodiment of the present invention.
# 1 to VC-3 MF at SDH frame reception when virtual concatenation is configured by # 3
FIG. 8 is a diagram showing transition of the I value, and FIGS. 8 to 11 are diagrams showing states of the write MFI value management memory 83 and the write completion flag shown in FIG. The operation of this embodiment will be described with reference to the specific examples shown in FIGS. In the following description, it is assumed that when the third frame is received, the MFI out-of-sync alarm of VC-3 # 3 is detected, and the MFI value is detected again in the fifth frame.

Phase adjustment has already been completed for the first frame,
Since it is assumed that the reading from the phase adjustment memory 6 has started, the head MFI values are all the same. In the description of this embodiment, the head MFI value is assumed to be "2". Also, the write completion flags are VC-3 # 1 to VC-3 #.
Up to 3, all are set to "1".

In the first frame, VC-3 # 1 to VC-
3 # 3 receives the MFI values “5”, “7”, “4”, and therefore updates the final MFI value to these values. In the second frame, since the reading from the phase adjustment memory 6 is performed, the start MFI value is updated (“2” → “3”), and the final MFI value is received.
To update.

In the third frame, the VC-3 # 3 detects the MFI out-of-sync alarm, so the write MF is executed.
The valid / invalid bit of VC-3 # 3 of the I value management memory 83 is set to invalid. VC-3 # 1, VC-3 # 2
Is the same as the processing of the second frame. As for the fourth frame, the MFI value is not rediscovered in VC-3 # 3, and therefore the processing related to VC-3 # 3 is not executed. The VC-3 # 1 and VC-3 # 2 are similar to the processing of the second frame (see FIG. 8).

M in VC-3 # 3 of the fifth frame
The case where the re-detected values of FI are three, "2", "10", and "12" will be described. When the re-detected MFI value is "2", the valid / invalid bit of VC-3 # 3 is set to valid, and the received MFI value "2" is written to MF.
The head / final MFI value of the I value management memory 83 is set.
The write completion flag is VC-3 # that has detected the alarm.
Write completion is set to VC-3 # 1 and VC-3 # 2 except for 3.

Thereafter, the VC-3 # 3 which detected the alarm
, The reception of the MFI value “3” is monitored. This MF
The I value “3” indicates that normal VC-3 # 1 and VC-3 #
It is the first MFI value of 2, and either one is selected and used. Since the processing of VC-3 # 1 and VC-3 # 2 is the same as that of the second frame, the description thereof will be omitted.

The sixth frame is M in VC-3 # 3.
Since the FI value “3” is received, the final MFI value is updated to “3” and the write completion flag of VC-3 # 3 is set to “1”. Since all the write completion flags of VC-3 # 1 to VC-3 # 3 have become “1”, the write completion signal is sent to start reading from the phase adjustment memory 6.
At that time, the read address is VC− with the MFI value “3”.
The address management unit 7 indicates the area where 3 is stored.
And the read addresses of VC-3 # 1 to VC-3 # 3 are updated. The head MFI value of VC-3 # 3 is also updated to "3" (see FIG. 9).

When the re-detected MFI value is "10", the valid / invalid bit of VC-3 # 3 is set to valid, the received MFI value "10" is written, and the head / final of the MFI value management memory 83 is written. Set to MFI value. VC-3
For # 2, the first MFI value is "3" and the last MFI value is
Since the FI value is “11”, it means that the MFI value “10” is received. Therefore, the write completion flag sets "1" to VC-3 # 2 and VC-3 # 3. Write MFI for VC-3 # 1 and VC-3 # 2
The processing of the value management memory 83 is the same as that of the case where the second frame is received, and therefore its explanation is omitted.

When the sixth frame is received, each VC-3
The write MFI value management memory 83 is updated, and since the MFI value “10” is received in VC-3 # 1, the write completion flag is set to “1”. At this time, since the write completion flags have been set for VC-3 # 1 to VC-3 # 3, the write completion signal is sent to start reading from the phase adjustment memory 6.

At this time, the read address is the MFI value "1".
To indicate the area where the VC-3 with "0" is stored,
The address management unit 7 is notified and VC-3 # 1 to VC-3
The read address of # 3 is updated. First M of VC-3 # 1 and VC-3 # 2 of write MFI value management memory
The FI value is also updated to "10" (see FIG. 10).

When the re-detected MFI value is "12", the valid / invalid bit of VC-3 # 3 is set to valid, the received MFI value "12" is written, and the head / final of the MFI value management memory 83 is written. Set to MFI value. VC-3
When it is confirmed whether or not the MFI value “12” is received for # 1 and VC-3 # 2, the head M of each is checked.
The FI value and the final MFI value are (“3”, “9”),
Since it is (“3”, “11”), the write completion flag is set only in VC-3 # 3.

In the sixth frame, only the updating process of the write MFI value management memory 83 is performed. 7th frame is VC-3
Since the MFI value "12" is received in # 2, the write completion flag is set. VC-3 # 1 to VC-3
Since the write completion flag is not set in all # 3, the reading from the phase adjustment memory 6 is not started.

The eighth frame is M-3 in VC-3 # 1.
Since the FI value “12” has been received, the write completion flag is set. Since all of the write completion flags have been set, the address management unit 7 is notified so that the read address indicates the area in which the VC-3 having the MFI value “12” is stored, and the VC-3 # 1 to VC-3 # are notified. The read address of 3 is updated. VC-of the write MFI value management memory 83
The head MFI values of 3 # 1 and VC-3 # 2 are also updated to "12" (see FIG. 11).

In this embodiment, the VC-3 is multiplexed on the STM-48. However, the present invention is not limited to this, and the STM-48 is an STM-12 or STM-3.
Etc., VC-3 can be replaced with VC-4 etc.

As described above, conventionally, when an MFI synchronization alarm is detected in a certain VC-3 that constitutes virtual concatenation, each VC when the MFI is re-detected.
While the phase adjustment was started based on the MFI value of -3, in the present embodiment, the normal VC-3 in which the MFI synchronization alarm is not detected is written in the phase adjustment memory 6 and the phase adjustment memory is also written. 6 The MFI value of the data written inside is managed, and the phase is adjusted using the re-detected MFI value and the managed MFI value, so that virtual concatenation is configured. V
When an MFI synchronization alarm is detected for C-3,
Compared with the conventional technique, the phase adjustment can be completed at high speed and the data reading can be restarted.

FIG. 12 is a block diagram showing the configuration of the re-phase adjusting section of the phase adjusting circuit according to another embodiment of the present invention.
In FIG. 12, a rephase adjusting unit 10 according to another embodiment of the present invention includes an MFI error detecting unit 101 and a phase determining unit 102.
2 has the same configuration as that of the re-phase adjusting unit 8 according to the embodiment of the present invention except that is provided, and the same components are designated by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

While the MFI error detection unit 101 detects the MFI synchronization alarm and adjusts the phase again, another VFI is detected.
In C-3, it is detected whether an MFI synchronization alarm has occurred. When an alarm occurs in a plurality of VC-3s, the phase determination unit 102 uses the re-detected MFI values of those VC-3s to arrive the earliest among the VC-3s in which the alarms occurred. Determine the VC-3 that is present.

The operation of the re-phase adjusting unit 10 according to another embodiment of the present invention will be described with reference to FIG. still,
The process of detecting the MFI out-of-sync alarm and performing the phase adjustment again is the same as that of the above-described embodiment of the present invention, and therefore its explanation is omitted.

While performing the phase adjustment again, another VC
-3, if an MFI out-of-sync alarm is detected, M
The FI error detection unit 101 interrupts the phase adjustment processing up to that point, and the phase determination unit 102 receives the MFI value of the VC-3 in which the MFI synchronization alarm was first generated and the MFI value of the VC-3 in which the MFI synchronization alarm was generated next. And notify.

The phase determination unit 102 uses the above two MFIs.
Refer to the value to determine which is arriving earlier. For example, the MFI value of VC-3 # 1 is A, VC-3
If the MFI value of # 2 is B (A> B), and if A−B <phase adjustable range, it means that VC-3 # 1 has arrived earlier, and B + 4096−A <phase adjustable range. If so, it means that VC-3 # 2 has arrived early. When A and B are equal, it means that they arrive at the same timing. If none of the above conditions are met, the phase adjustment is not possible and a phase adjustment error is issued and the process ends.

After the processing of the phase determination unit 102, the VC-3 in which the MFI out-of-sync alarm is detected is compared with the head MFI value of the normal VC-3 (step S9 in FIG. 6), and the phase determination unit is executed. V whose phase is judged to be early is 102
The process of determining whether or not the MFI value of C-3 and the other channels (CH) have received the above MFI value (step S12 in FIG. 6) is performed in parallel.

In the present embodiment, while the MFI synchronization alarm is detected and the re-phase adjustment is performed, the occurrence of the MFI synchronization alarm in another VC-3 is monitored and the phase is detected when the alarm is detected. By interrupting the adjustment processing, determining which VC-3 arrives earlier for the alarmed VC-3s, and restarting the phase adjustment processing, the phase synchronization alarms are generated in the VCs. When it occurs, there is a new effect that the phase adjustment can be performed at high speed as compared with the conventional technique.

[0079]

As described above, according to the present invention, the normal VC-3 in which the MFI synchronization alarm is not detected is written in the phase adjustment memory and the MFI value of the data written in the phase adjustment memory. Is controlled and the phase is adjusted using the re-detected MFI value and the managed MFI value, the effect that the phase adjustment can be completed at high speed and the data reading can be restarted is obtained. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a rephase adjusting unit in FIG.

FIG. 3 is an STM-4 in the phase adjustment memory shown in FIG.
8 is a diagram showing a configuration in the case of processing data in which VC-3 is multiplexed in 8; FIG.

FIG. 4 is a diagram showing a configuration of a write MFI value management memory shown in FIG.

FIG. 5 shows whether the write MFI value management memory shown in FIG.
It is a figure which shows an example of the bit which shows invalidity.

FIG. 6 is a flowchart showing the operation of the phase adjustment circuit according to the embodiment of the present invention.

FIG. 7 shows VC-3 # 1 to V in one embodiment of the present invention.
It is a figure which shows the transition of the MFI value at the time of SDH frame reception at the time of comprising a virtual concatenation by C-3 # 3.

FIG. 8 is a diagram showing states of a write MFI value management memory and a write completion flag shown in FIG.

9 is a diagram showing states of a write MFI value management memory and a write completion flag shown in FIG.

10 is a diagram showing states of a write MFI value management memory and a write completion flag shown in FIG.

11 is a diagram showing states of a write MFI value management memory and a write completion flag shown in FIG.

FIG. 12 is a block diagram showing a configuration of a re-phase adjusting unit of a phase adjusting circuit according to another embodiment of the present invention.

FIG. 13 is an STM-in which VC-3 is multiplexed in 48 channels.
It is a figure which shows the frame format of 48.

FIG. 14 is a diagram showing a transfer path of a conventional virtual concatenation.

FIG. 15 is a diagram showing a VC-3 path overhead format.

FIG. 16 is a diagram showing a phase difference when a data string is mapped to two VC-3s and transferred.

FIG. 17 is a diagram showing a phase difference when a data string is mapped to two VC-3s and transferred.

[Explanation of symbols]

1 SDH termination processing unit 2 MFI detector 3 MFI synchronization management unit 4 Phase adjuster 5 Write controller 6 Phase adjustment memory 7 Address management section 8,10 Re-phase adjustment unit 9 Read controller 81 Reception MFI determination processing unit 82 Write Complete Flag Update Processing Unit 83 Write MFI value management memory 84 Write MFI value update processing unit 101 MFI error detector 102 phase determination unit

Claims (6)

[Claims] 1. In input data such that one band is provided by a plurality of virtual containers by virtual concatenation, MFI (M) for managing the temporal arrangement of the plurality of virtual containers.
A phase adjustment circuit for performing phase adjustment when the continuity of the values of the multi-frame indicators is lost, and a means for writing to the phase adjustment memory about a normal virtual container in which an MFI synchronization alarm is not detected, and the phase adjustment. MF of data written in the memory
A phase adjustment circuit comprising: means for managing an I value; and means for performing a phase adjustment using the re-detected MFI value and the managed MFI value. 2. Means for monitoring the occurrence of the MFI synchronization alarm in another virtual container while detecting the MFI synchronization alarm and performing rephase adjustment, and the phase when the MFI synchronization alarm is detected. The means for interrupting the adjustment processing and determining which virtual container arrives earlier among the plurality of virtual containers in which the MFI synchronization alarm has occurred, and restarting the phase adjustment processing. Phase adjustment circuit. 3. The virtual container is VC (Vi
The phase adjusting circuit according to claim 1 or 2, wherein the phase adjusting circuit is any one of the following: r. 4. In input data such that one band is provided by a plurality of virtual containers by virtual concatenation, MFI (M) for managing the temporal arrangement of the plurality of virtual containers.
A method for performing phase adjustment when the continuity of the values is lost, wherein the normal virtual container in which the MFI synchronization alarm is not detected is written in the phase adjustment memory and is stored in the phase adjustment memory. A phase adjusting method comprising: managing an MFI value of written data, and performing a phase adjustment using the redetected MFI value and the managed MFI value. 5. The generation of the MFI synchronization alarm in another virtual container is monitored while the MFI synchronization alarm is detected and rephase adjustment is performed, and the MFI synchronization alarm is monitored.
When the synchronization alarm is detected, the phase adjustment process is interrupted, and it is determined which virtual container is arriving earlier among the plurality of virtual containers in which the MFI synchronization alarm has occurred, and the phase adjustment process is restarted. The phase adjustment method according to claim 4, wherein 6. The virtual container is VC (Vi
6. The phase adjusting method according to claim 4 or 5, wherein the phase adjusting method is one of a virtual contour) -3 and a VC-4.