JPH0993283A - Line setting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent delay in data and a clock after changeover and increase in duty fluctuation by configuring a changeover switch with a polarity inversion gate and a polarity inversion switch group. SOLUTION: The system is provided with 1st and 2nd gate elements 411 , 412 or 451 , 452 receiving two input signals A, B at respective one-side inputs and receiving two kinds of control signals at respective other-side inputs. Furthermore, a 2-1 switch consisting of a 3rd gate element 42 or 46 coupling outputs of the 1st and 2nd gate elements is formed. When either of the control signals is significant, the 3rd gate element, provides an output signal resulting from selecting either of the two inputs A, B based on the control signal. Then each gate element is made up of polarity inversion gate elements to inverts an input signal for its output to form the line changeover switch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching function in a transmission device, and more particularly to a switch configuration method for switching lines, a switching control method, and a self-check method at the time of line switching.

In recent years, along with the demand for higher performance, larger scale, higher speed, and higher reliability of transmission line networks, it is necessary to switch lines in multiple stages when setting transmission lines or performing redundant switching. There is.

In the line switching of the transmission device, the lines are switched in a matrix by having a plurality of space switches. At this time, the line switching includes a redundant switching function to the backup line, and the redundant switching is performed. Includes one-to-one redundant switching and one-to-many redundant switching.

In such a case, the line setting method should be such that even if multistage switching is performed, the amount of delay of data and clock and duty fluctuation are small, and line switching can be checked. Is.

[0005]

2. Description of the Related Art FIG. 16 shows a basic configuration of a conventional transmission line network to which the present invention is applied _.
Shows a configuration in which connection 1 ₂ by a transmission path 2 _1, 2 _2. Each station is provided with a line setting unit 3 for transmitting / receiving to / from a transmission line by a multiplexed signal, and with a multiplexing / demultiplexing / switching unit 4 for multiplexing data from a plurality of lines. The circuit is passed to the line setting unit 3, the multiplexed signal from the line setting unit 3 is separated and sent to each line, and the line switching function is performed.

In the line setting section shown in FIG. 16,
A lot of line changeover switches with redundant changeover function and matrix switches are used in combination for line setting.

FIG. 17 shows the configuration of a conventional line changeover switch with a redundancy changeover function, which is a 1: m redundancy changeover section 11 consisting of m 2-1 switches.
And a redundant switching unit on the input side provided with n sets of 1: 1 redundant switching units 12 including m 2-1 switches, and m ×
a line switching unit 13 composed of an n matrix switch,
1: 1 redundant switching unit 1 composed of n 1-2 switches
4 and a 1: n redundancy switching unit 1 composed of n-1 switches
5 and 5 are connected in series.

In the line changeover switch with redundant changeover function shown in FIG. 17, the 1: m redundant changeover section 11 performs 1: m redundant changeover between m even-numbered input lines and input spare lines. 1: 1 redundancy switching unit 12 and m odd-numbered input lines and 1: m
1: 1 redundancy switching is performed between the outputs of the respective 2-1 switches forming the redundancy switching unit 11.

Further, the line switching unit 13 selectively connects between the m inputs and the n outputs from the n sets of 1: 1 redundancy switching units 12, and the 1: 1 redundancy switching unit 14 performs connection. , 1: 1 redundant switching is performed between the n odd-numbered output lines and the n even-numbered output lines, and the 1: n redundant switching unit 15 outputs n even-numbered output lines. 1: n redundancy switching is performed with the protection line.

FIG. 18 shows a concrete example of a conventional line changeover switch having a redundancy changeover function.
An example of x5 switching is shown. Further, FIG. 19 shows a control table of a conventional line changeover switch having a redundancy changeover function, and shows a setting portion of a selected line 1 for 5 × 5 changeover.

In the line changeover switch with redundant changeover function shown in FIG. 18, a 1: 2 redundant changeover section 11A consisting of two 2-1 switches for performing redundant changeover between the even-numbered line and the line 5 and an odd number. Second line and 1:
2 Redundant switching on the input side provided with 5 sets of 1: 1 redundant switching section 12A consisting of two 2-1 switches for performing redundant switching between the outputs of the respective 2-1 switches constituting the 2 redundant switching section 11A Section, and a line switching unit 13A composed of a 5 × 5 matrix switch for selectively connecting 5 inputs from each of the 5 sets of redundant switching units on the input side and 5 outputs. Connecting.

Further, a 1: 1 redundancy switching section 14A consisting of two 2-1 switches for performing 1: 1 redundancy switching between the odd-numbered output and the even-numbered output of the line switching section 13A and 1: 1. From the 1: 2 redundancy switching unit 15A including the 3-1 switch that performs 1: 2 redundancy switching between the output of each 2-1 switch that configures the redundancy switching unit 14A and the fifth output of the line switching unit 13A. The redundant switching unit on the output side is serially connected to select line 1
Output ~ 5.

At this time, for the selected line 1, as shown in FIG. 19, the 1: 2 redundancy switching unit 1 is controlled by the control A signal.
1A is selected, the control B signal switches the 1: 1 redundancy switching unit 12A, and the control C signal switches the line switching unit 13A.
The 1: 1 redundancy switching section 14A is switched by a signal, and the 1: 2 redundancy switching section 15 is controlled by a control E signal.
By switching A, lines 1 to 5 can be selected and output to the selected line 1. The same applies to other selected lines.

FIG. 20 shows a matrix switch composed of conventional 2-1 switches.
−1 switches 21 _{1 to} 21 ₇ are sequentially connected in multiple stages in an inverted tree shape to form an 8-1 switch, and eight 8-1 switches 22 _{1 to} 22 ₈ are used in parallel and each 8−
Two control signals for each stage are generated by three control signals for each switch.
8x8 by controlling the switching of one switch
It is shown that a switch has been configured.

FIG. 21 shows the structure of a conventional 2-1 switch, in which (a) is a 2-1 switch having an AND-OR gate structure, and (B) is a 2-1 switch having an OR-and-gate structure. It is a switch.

In the 2-1 switch having the AND / OR gate configuration shown in FIG. 21A, the inputs A and B are connected to one input of the _two AND gates 25 _{1 and} 25 ₂ , and the outputs of the respective gates are connected. Are connected by an OR gate 26. Then, the positive control signal is applied to one AND gate 25 ₁ and the control signal is inverted by the inverter 27 and applied to the other AND gate 35 ₂ .
Either one of the inputs A and B is selected and output from the OR gate 26 according to the control signal "1" or "0".

In the OR-and-gate 2-1 switch shown in FIG. 21B, inputs A and B are connected to one input of _two OR gates 31 _{1 and} 31 ₂ , and
The respective outputs are combined by the AND gate 32. Then, the negative polarity control signal is applied to one of the OR gates 31 ₁ , and the control signal is inverted by the inverter 33 and applied to the other OR gate 31 ₂ , so that the control signals “1” and “0” are given. Either one of the inputs A and B is selected and output from the OR gate 32.

FIG. 22 shows a conventional matrix switch composed of AND or OR gates.
The case where eight switches are formed is shown. Input data 1
8 to 8 are connected to one input of _eight AND gates 25 _{1 to} 25 ₈ and the 3-8 decoder 28 expands the 3-bit control signals 1-1 to 1-3 to control 8 positive polarities. the signal, and controls the other input of the aND gate 25 _to 253 _8, by generating a select data 1 by combining the outputs of the aND gates 25 _to 253 ₈ in the OR gate 26A, to form a multiplexer .

Further eight multiplexers 29 _{1 to} 29
_{An 8} × 8 matrix switch is formed by controlling each ₈ with a 3-bit control signal and outputting the select data 1-8.

FIG. 23 shows a conventional matrix switch composed of OR-and-gates, which is 8 ×
The case where eight switches are formed is shown. Input data 1
8 to 8 are connected to one input of ₈ OR gates 31 _{1 to} 31 ₈ and eight negative control signals obtained by expanding the 3-bit control signals 1-1 to 1-3 by the 3-8 decoder 34. by, and controls the other input of each OR gate 31 _{1-31 8,} by generating a select data 1 by combining the outputs of the OR gates 31 ₁ to 31 ₈ in the aND gate 32A, to form a multiplexer.

Further eight multiplexers 35 _{1 to} 35
_{An 8} × 8 matrix switch is formed by arranging ₈ inputs in parallel to provide input data 1 to 8 and controlling each multiplexer by a 3-bit control signal to output select data 1 to 8. It

[0022]

The conventional switch, as shown in FIGS. 20 to 23, is composed of a gate of the same polarity and a switch group of the same polarity. In general, the delay amount of elements such as AND gates or OR gates that make up a switch is
Since one of the rising edge and the falling edge tends to be large, there is a problem that the larger the switch size and the number of stages, the larger the delay amount of data and clock and the duty fluctuation after line switching.

The conventional line changeover switch with redundant changeover function has a structure in which the redundant changeover switch and the matrix switch are serially connected, as shown in FIGS. Therefore, when these switches are composed of gates of the same polarity and a group of switches of the same polarity, there is a problem in that the delay amount and duty fluctuation of the data and clock to be switched also increase.

Further, since the conventional line switch has a small number of lines and a low operation speed, it is not necessary to check that the switching has been normally performed. However, it is necessary to check the line switching due to the increase in the number of lines, the speeding up of the lines, and the increase in reliability, but conventionally, no checking means has been proposed in such a case.

The present invention is intended to solve such a problem of the prior art. Even when a switch used for line switching in a transmission device is large-scaled and has multiple stages, data and data after switching are changed. The purpose is to prevent an increase in clock delay amount and duty fluctuation.

Further, according to the present invention, in the line changeover switch having the redundancy changing function, the delay of the data and the clock after the change is caused by the increase of the number of stages of the changeover switch based on the fact that the redundancy changeover and the matrix changeover are performed by the respective switches. The purpose is to prevent an increase in quantity and duty fluctuation.

It is another object of the present invention to provide a line switching switch with a self-check function at the time of line switching to achieve high reliability of line switching.

[0028]

According to the present invention, a switch used for line switching in a transmission device is increased in scale by configuring the changeover switch with a polarity reversal gate or a group of polarity reversal switches, Even when the number of stages is increased, it is possible to prevent an increase in delay amount of data and clock and duty fluctuation after switching.

Further, in the line changeover switch having the redundant changeover function, the redundant changeover and the matrix changeover are carried out by a control signal in which each control signal is integrated, so that the line changeover can be realized by a single switch, and after the changeover, It is possible to prevent an increase in the amount of delay of data or clock and variation in duty in the above.

Further, in the present invention, the line changeover switch is provided with a self-check function at the time of line changeover, thereby realizing high reliability of line changeover.

Specific means for solving the problems of the present invention will be listed below.

(1) First and second gate elements (41 _1, 41) to which two input signals A and B are applied to one input and two kinds of control signals are applied to the other input, respectively.
₂ or 45 _1, 45 ₂ ) and a third gate element (42 or 4) for coupling the outputs of the first and second gate elements.
6) and, when either one of the control signals becomes significant, an output signal in which one of the two inputs A and B is selected from the output of the third gate element is generated in accordance with this control signal. In the 2-1 switch, each gate element is composed of a polarity inverting gate element that inverts the polarity of the input signal and outputs the inverted signal.

(2) In the case of (1), a plurality of line changeover switches (53 _{1 to} 53 ₁₅ ) are used to sequentially connect in a reverse dendritic manner in multiple stages, and each line changeover switch of the first stage is connected. By giving two different input signals and controlling to select and output either one of the inputs by the line selector switch of each stage by the control signal corresponding to each stage, one of the plurality of input signals is output. To generate an output signal.

(3) One input for each of a plurality of input signals
To the other input
A plurality of two-input gate elements (41₁ ~ 41₈ Or
45 ₁ ~ 45₈ ) And the outputs of multiple 2-input gate elements
Or a multi-input gate element (42A or 46A)
And one of the control signals becomes significant.
According to this control signal,
Output that selects any one of multiple input signals from the output
Each gate element in a multiplexer that generates a signal
Polarity inversion gate that inverts the polarity of the input signal and outputs
It is composed of elements.

(4) In the case of (3), switch the line
Plural (51₁ ~ 51₈ Or 52 ₁ ~ 52₈ ) Used,
Each line selector switch to the corresponding control signal
Therefore, control each line selector switch
By selecting and outputting one input, multiple input signals
Signal to generate an output signal at a plurality of outputs.

(5) In the case of (4), a redundant switching control signal for performing redundant switching for a plurality of input signals, a switching control signal for switching input signals after redundant switching, and a line switching Line switching control signal generation unit (56) that generates a switching control signal for controlling switching to the line switching switch by taking a logic with a redundant switching control signal for performing redundant switching on the line signal of (6) to generate an output signal. Or 56A), and the line switch (55 or 55A) performs redundant switching by collective switching control according to this switching control signal.

(6) For the line changeover switch in the cases of (5), a check code inserting section (57) for inserting a check code consisting of a fixed value into the input signal is provided corresponding to a plurality of input signals, and The check code inserted in the output signal is compared with a predetermined check code to detect an error, and a switching check unit (58) for checking the switching in the line switching switch by the error is provided for each output signal. Set up.

(7) In the cases of (6), the check code is composed of a fixed value inserted in the unused overhead in the overhead byte in the data frame format.

(8) In the cases of (7), a fixed value is used as the switching control signal.

(9) In the case of (6), the check code insertion section (57) prohibits the insertion of the check code when the input signal is not frame-synchronized or when the disconnection of the input signal is detected. .

(10) In the case of (6), when the check code insertion section (57) cannot achieve frame synchronization in the input signal or when the disconnection of the input signal is detected,
AIS is inserted into the input signal and transmitted.

In the cases of (11) and (6), the switching check unit (58) prohibits the switching check operation when the input signal is not frame-synchronized or when the disconnection of the input signal is detected.

(12) In the case of (6), when the switching check section (58) cannot establish frame synchronization in the input signal or when the disconnection of the input signal is detected, the AIS is inserted in the output signal. Send out.

(13) In the case of (7), at the switching check unit (58), at the end of the switching check for the input signal, the inserted check code is erased to restore the original overhead byte fixed data and output. To do.

In the cases (14) and (7), the switching check unit (58) inserts a check code when the switching signal is not synchronized with the input signal during the switching check operation or when the disconnection of the input signal is detected. Prohibit changes to the previous overhead byte data.

[0046]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment (1) of the present invention, showing a basic structure of a 2-1 switch, and (a) is a 2-1 switch having a NAND / NAND gate structure. , (B) are 2-1 switches having a NOR gate configuration.

In the 2-1 switch having the NAND / Nand gate configuration shown in FIG. 1A, the inputs A and B are connected to one input of the _two NAND gates 41 _{1 and} 41 ₂ , and the respective outputs are connected. They are connected by the NAND gate 42. Then, the control signal of positive polarity is applied to one NAND gate 41 ₁ , and the control signal is inverted by the inverter 43 and applied to the other NAND gate 41 ₂ , so that the control signal is "1" or "0". Either one of the inputs A and B is selected and output from the NAND gate 42.

In the 2-1 switch having the NOR gate structure shown in FIG. 1B, the inputs A and B are connected to one of the inputs of the _two NOR gates 45 _{1 and} 45 ₂ , and the outputs of the NOR gates are connected to each other. Connect at NOR gate 46. Then, the negative polarity control signal is applied to one NOR gate 45 ₁ and the control signal is inverted by the inverter 47 and applied to the other OR gate 45 ₂ so that the control signal is “1” or “0”. Either one of the inputs A and B is selected and output from the NOR gate 46.

In the 2-1 switch shown in FIG. 1, since the polarity of the signal is inverted between the switch at the front stage and the switch at the rear stage, there is a rise delay amount of the signal due to the characteristics of the element after passing through the switch. It is possible to suppress the relative variation in the rising and falling delay amounts based on the difference in the falling delay amount, and to reduce the delay amount and duty fluctuation of the data and clock after passing through the switch.

2 and 3 show an embodiment (2) of the present invention. FIG. 2 shows the structure of a multiplexer having a NAND / NAND gate structure, and FIG. 3 shows the structure of a multiplexer having a NOR gate.

In FIG. 2, eight pieces of input data 1 to 8
Nando Gate 41₁ ~ 41₈ Connect to one input of
Each NAND gate is controlled by the positive polarity switching control signals 1 to 8.
41 ₁ ~ 41₈ Connect to the other input of
NAND gate 41₁ ~ 41₈ Output of the NAND gate 42A
, And generate select data.
Form a plexiplex.

In FIG. 3, input data 1 to 8 are connected to one input of _eight NOR gates 45 _{1 to} 458, and each of the NOR gates 45 is controlled by the negative polarity switching control signals 1 to 8.
While connected to the other input of _{1-45 8} by generating the select data by combining the outputs of the NOR gates 45 ₁ to 45 ₈ in NOR gate 46A, to form a multiplexer.

FIGS. 4 and 5 show the embodiment (3) of the present invention. FIG. 4 shows the structure of a matrix switch having a NAND / NAND gate structure, and shows a case where an 8 × 8 matrix switch is composed by using eight multiplexers having a NAND / NAND gate structure. FIG. 5 shows the structure of a matrix switch having a NOR gate structure, which is 8 × 8 using eight multiplexers having a NOR gate structure.
The matrix switch of FIG.

In FIG. 4, eight multiplexers 51 are provided.
The input of _{1-51 8,} together provide data 1-8, respectively, in each multiplexer, 3-8 decoder 4
An 8 × 8 matrix switch is formed by controlling the NAND gates and NAND gates with eight positive polarity switching control signals, which are three-bit control signals expanded by eight, and outputting select data. .

In FIG. 5, eight multiplexers 52 are provided.
_{1-52 8} with each providing input data 1-8 to the input of, in each multiplexer, the eight negative switching control signal obtained by developing the control signal of 3 bits by the 3-8 decoder 49, respectively Noah An 8 × 8 matrix switch is formed by controlling the NOR gate and outputting select data.

As described above, also in the case of the multiplexer and the matrix switch, the polarity inversion gate is used to configure that the polarity of the signal is inverted between the switch in the front stage and the switch in the rear stage. It is possible to suppress the relative variation in the delay amount between the rising edge and the falling edge of the signal, and it is possible to reduce the delay amount of the data and the clock after passing through the switch and the duty fluctuation.

FIG. 6 shows an embodiment (4) of the present invention, showing a multi-stage switch constituted by using a polarity reversal 2-1 switch, and an example in which a 16-1 switch is constituted. ing. In the figure, each 2-1 switch 53 _{1 to} 53
₁₅ has a structure as shown in FIGS. 1 (a) and 1 (b).

Data (1, 2), (3, 4), ..., (1
5,16) respectively 2-1 switches 53 _1, 53 _{2, ...,}
53 In _8, selected in accordance with the control 1 signal, 2-1 switch (53 _1, 53 _2), (53 _3, 53 _4), ..., (5
The output of 3 _7, 53 ₈ ) is respectively 2-1 switch 53 _9, 5
3 _10, ... _, 53 ₁₂ are selected according to the control 2 signal, and 2-1 switches (53 _9, 53 ₁₀ ), (53 _11, 53
The output of ₁₂ ) is selected by the 2-1 switches 53 _13, 53 ₁₄ according to the control 3 signal, and the 2-1 switch 5
The output of 3 _13, 53 ₁₄ at the 2-1 switch 53 ₁₅
Data 1 by selecting according to the control 4 signal
It is possible to realize a 16-1 switch that selects any one of 2, 3, ..., 16 and outputs it as select data.

Further, by using a plurality of multistage switches configured by using the polarity inversion 2-1 switch as described above, and by configuring the switch in the same manner as the matrix switch shown in FIG. 20, the polarity inversion 2-1 switch is obtained. It is possible to configure a matrix switch using.

Also in the case of such a multiplexer or a matrix switch which performs multi-stage switching, the switch of each stage is constructed by using the polarity inversion 2-1 switch, so that the delay of the rising and falling of the signal after passing through the switch is delayed. It is possible to suppress the relative variation in the amount, and it is possible to reduce the delay amount and duty variation of the data and the clock after passing through the switch.

FIGS. 7, 8 and 9 show an embodiment of the present invention.
(5) is shown. FIG. 7 shows the configuration of a line changeover switch with a redundant changeover function for performing collective changeover control, and illustrates a case where 5 × 5 changeover is performed. In the figure, 55 is a 5 × 5 matrix switch which constitutes a line switching unit, and 56 is a line switching control signal generating unit consisting of five switches. Further, FIG. 8 shows a control table for collective switching of the line switching switch with the redundant switching function, and shows a setting portion of the selected line 1 for 5 × 5 switching.

In the line switching switch with redundant switching function for performing batch switching control shown in FIG. 7, a control A signal and a control B signal for performing redundant switching on the input side of the line switching unit, and a line switching unit. From the control C signal for switching the line and the control D signal and control E signal for performing redundant switching on the output side of the line switching unit, the line control signal generating unit 56 collectively takes a logic to switch. By generating a control signal and controlling the 5 × 5 matrix switch 55, line switching similar to that of the conventional line switching switch with redundant switching function shown in FIG. 18 can be performed. The same applies to other selected lines.

FIG. 9 shows a general structure of a line changeover switch having a redundant changeover function for performing collective changeover control, and shows a case of performing m × n changeover. In the figure, 55A denotes a line switching unit m ×
n matrix switch. Reference numeral 56A denotes a line switching control signal generation unit consisting of n pieces, which collectively takes a logic for the control signal for redundant switching and the control signals A to Z for line switching to generate a switching control signal. By generating and controlling the m × n matrix switch 55A, redundant switching is performed between the lines 1 to m on the input side and the selected lines 1 to n on the output side.

As described above, in the case of the line changeover switch with the redundant changeover function for performing the collective changeover control, the number of switch stages can be reduced by using only the matrix switch as the changeover switch.
By configuring the matrix switch in this case with a group of polarity reversing switches, it is possible to suppress the amount of delay of data and clocks after passing through the switches and the duty variation.

10 to 12 show an embodiment (6) of the present invention.
And shows a case where the line switching unit checks the line switching. FIG.
Shows the configuration at the time of line switching check, and shows the case where it is applied to an m × n matrix switch.
The same parts as those in FIG. 9 are indicated by the same numbers. 57
Is a check code insertion unit for inserting a code for line switching check, and 58 is a switching check unit for checking the switching state in the line switching unit.

As shown in FIG. 10, a line check code insertion unit for inserting a code for checking line switching (line switching check code) is provided in the preceding stage of the line switching unit (position before line switching). A line switching check unit for checking the line switching state is provided at the subsequent stage (position after line switching). The line check code insertion unit includes a check code insertion unit 57 for each line. The line switching check unit includes a switching check unit 58 for each selected line.

FIG. 11 shows the structure of the check code insertion unit, which is shown to include a synchronization detection unit 61, a timing generation unit 62, and a check code writing unit 63. The timing generator 62 divides the input clock to generate the check code insertion timing. The synchronization detector 61 detects the synchronization pattern and the synchronization timing to establish synchronization, and the timing generator 62 controls the timing generation. The check code writing unit 63 inserts the line switching check code at a predetermined position in the data frame at the synchronized timing.

As the line switching check code, the switching control signal generated by the line switching control signal generating unit 56A is used, and in the check code writing unit 63, it is inserted as a fixed value for each line in the overhead byte portion in the data frame format. To do.

FIG. 12 shows the configuration of the switching check unit, which includes a synchronization detection unit 71 and a timing generation unit 7.
2, it is shown that a check code detection unit 73, a check code comparison unit 74, and a switching check error detection unit 75 are provided.

The timing generator 72 divides the input clock to generate the timing at which the check code is inserted. The synchronization detector 71 detects the synchronization pattern and the synchronization timing to establish synchronization,
The timing generation unit 72 controls timing generation. The check code detector 73 extracts the check code in the data frame format at the synchronized timing.

The check code comparing section 74 compares the check code extracted by the check code detecting section 73 with the switching control signal from the line switching control signal generating section 56A. The switching check error detection unit 75 takes a protection as an error and generates a switching error detection signal when an error is detected more than a specified number of times within the detection pulse period based on the comparison result of the check code comparison unit 74. .

FIG. 13 shows an example of the data frame format, which is the STM according to the CCITT recommendation.
-1 frame format is illustrated. An unused overhead byte portion (CCITT.STM) shown by hatching in the illustrated data frame format.
In the example of -1 frame format, all "1"),
By inserting the line switching check code,
Line switching can be checked without affecting overhead bytes or data.

FIG. 14 shows a concrete example of the structure of the check code insertion section. The same elements as those in FIG. 11 are shown by the same numbers, 64 is a disconnection detection section for detecting a line disconnection, and 65 is an alarm. AIS for inserting signal (AIS)
It is an insertion part. Further, FIG. 15 shows a specific configuration example of the switching check unit, in which the same components as those in FIG. 12 are indicated by the same numbers, 76 is a disconnection detection unit for detecting a line disconnection, and 77 is an input data in the input data. A check code erasing unit for erasing the line switching check code, and 78 is an AIS inserting unit for inserting an alarm signal (AIS).

In the switching check unit, the check code erasing unit 77 erases the inserted check code at the check code timing from the timing generating unit 72 and restores the overhead byte information inserted before the switching. By this, the line can be switched without changing the data to be transmitted before and after the line is switched.

In the check code insertion unit, the check code writing unit 63 detects that the synchronization detection unit 6 is out of synchronization.
When an out-of-sync signal is input from 1, the insertion of the check code for the input is prohibited. This is because the line switching check is unnecessary in the out-of-sync state,
This is to prevent the check code from being inserted and transmitted at a position other than the predetermined position in the data frame format.

By inputting the out-of-sync signal from the synchronization detecting section 61 to the AIS inserting section 65, when the out-of-sync state is inserted, the AIS is inserted and sent out, whereby the out-of-sync alarm can be issued.

In the switching check unit, when synchronization is lost,
By inputting the out-of-sync signal from the synchronization detection unit 71, the detection of the switching check error in the switching check error detection unit 75 is prohibited. This is because an error always occurs as a result of comparison by the check code comparison unit 74 when the synchronization is lost, but since the synchronization loss signal has already been output,
This is because it is not necessary to detect the switching check error again.

At the time of out-of-sync, by inputting an out-of-sync signal from the sync detecting section 71, the check code erasing section 77 prohibits erasing the check code and restoring the overhead byte information. This is an out-of-sync state, so deleting the check code causes unnecessary data changes, and because of an out-of-sync state, restoring overhead byte information also causes unnecessary data changes. This is because.

Further, at the time of out-of-synchronization, the out-of-synchronization signal from the synchronization detecting section 71 is inputted to the AIS inserting section 65 so that the AIS is inserted and transmitted, whereby the out-of-synchronization alarm can be issued.

In the check code insertion unit, when the disconnection of data or clock is detected, the disconnection detection signal from the disconnection detection unit 64 is input to the check code writing unit 63,
Prohibit insertion of check code. This is because line disconnection check is unnecessary in the disconnection detected state,
This is to prevent the check code from being inserted and transmitted.

Further, when a disconnection of data or a clock is detected, the disconnection detection signal from the disconnection detection unit 64 is input to the AIS insertion unit 65 so that the AIS is inserted and sent out to issue an alarm of these disconnection detections. be able to.

In the switching check unit, when the disconnection of data or clock is detected, the switching check error detection is prohibited by inputting the disconnection detection signal from the disconnection detection unit 74 to the switching check error detection unit 75. This is because when the disconnection is detected, the comparison result of the check code comparison unit 74 always causes an error, but since the disconnection detection signal has already been output, it is not necessary to perform the switching check error detection again.

Further, when the disconnection of data or clock is detected, the disconnection detection signal from the disconnection detector 74 is sent to the check code eraser 7.
By inputting in 7, the check code is erased,
Prohibit restoration of overhead byte information. Since this is a disconnection detection state, unnecessary data change is caused by erasing the check code, and because it is a disconnection detection state, unnecessary data change is also caused by restoration of overhead byte information. This is because

Furthermore, when data or clock loss is detected,
By inputting the disconnection detection signal from the disconnection detection unit 74 to the AIS insertion unit 78 and inserting and transmitting the AIS, these disconnection detection alarms can be issued.

[0085]

As described above, according to the present invention, the changeover switch is composed of the polarity reversing gate and the group of the polarity reversing switches, so that the delay amount of data or clock and the duty fluctuation at the time of line setting can be reduced. You can

Further, when performing redundant switching or matrix switching, control of the redundant switching and control signals for switching the lines are controlled by a switching control signal that collectively controls the switching of lines. This can be realized by a switch, and it is possible to reduce the amount of delay of data and clock and the duty fluctuation at the time of line setting.

Further, according to the present invention, since the line changeover switch can be provided with a line changeover check function, it is possible to realize high reliability of line changeover.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a 2-1 switch,
(a) shows a 2-1 switch having a NAND / Nand gate configuration, and (b) shows a 2-1 switch having a NOR gate configuration.

FIG. 2 is a diagram showing a configuration of a multiplexer having a NAND / NAND gate configuration.

FIG. 3 is a diagram showing a configuration of a multiplexer having a NOR gate configuration.

FIG. 4 is a diagram showing a configuration of a matrix switch having a NAND / NAND gate configuration.

FIG. 5 is a diagram showing a configuration of a matrix switch having a NOR gate configuration.

FIG. 6 is a diagram showing a multistage switch configured by using a polarity reversal 2-1 switch.

FIG. 7 is a diagram showing a configuration of a line changeover switch with a redundant changeover function for performing collective changeover control.

FIG. 8 is a diagram showing a control table for collective switching of line switching switches with a redundant switching function.

FIG. 9 is a diagram showing a general configuration of a line changeover switch having a redundant changeover function for performing collective changeover control.

FIG. 10 is a diagram showing a configuration during line switching check.

FIG. 11 is a diagram showing a configuration of a check code insertion unit.

FIG. 12 is a diagram showing a configuration of a switching check unit.

FIG. 13 is a diagram showing an example of a data frame format.

FIG. 14 is a diagram showing a specific configuration example of a check code insertion unit.

FIG. 15 is a diagram illustrating a specific configuration example of a switching check unit.

FIG. 16 is a diagram showing a basic configuration of a conventional transmission line network to which the present invention is applied.

FIG. 17 is a diagram showing a configuration of a conventional line changeover switch with a redundant changeover function.

FIG. 18 is a diagram showing a specific example of a conventional line changeover switch with a redundant changeover function.

FIG. 19 is a diagram showing a control table of a conventional line changeover switch with a redundant changeover function.

FIG. 20 is a diagram showing a matrix switch composed of conventional 2-1 switches.

FIG. 21 is a diagram showing a configuration of a conventional 2-1 switch, in which (a) shows a 2-1 switch having an AND or OR gate configuration, and (b) shows a 2-1 switch having an OR AND gate configuration. Show.

FIG. 22 is a diagram showing a conventional matrix switch composed of AND / OR gates.

FIG. 23 is a diagram showing a conventional matrix switch composed of OR-and-gates.

[Explanation of symbols]

41 _{1 to} 41 ₈ gate element 42 gate element 42A gate element 45 _{1 to} 45 ₈ gate element 46 gate element 46A gate element 51 _{1 to} 51 ₈ line changeover switch 52 _{1 to} 52 ₈ line changeover switch 53 _{1 to} 53 ₁₅ line changeover switch 55 line changeover switch 55A line changeover switch 56 line changeover control signal generation unit 56A line changeover control signal generation unit 57 check code insertion unit 58 changeover check unit

Claims (14)

[Claims] 1. A first and second gate element having two input signals A and B applied to one input and two kinds of control signals applied to the other input, respectively, and the first and second gate elements. A third gate element for coupling the outputs of the gate elements of the third gate element and the two inputs from the output of the third gate element in response to the control signal when one of the control signals becomes significant. A 2-1 switch for generating an output signal by selecting either A or B, wherein each of the gate elements comprises a polarity reversal gate element for inverting the polarity of the input signal and outputting the inverted signal. . 2. A plurality of line changeover switches according to claim 1 are sequentially connected in a multi-stage in a reverse dendritic manner, and two different input signals are given to each line changeover switch of the first stage. By controlling to select and output one of the inputs in the line selector switch of each stage by the control signal corresponding to the stage,
A line changeover switch, wherein any one of a plurality of input signals is selected to generate an output signal. 3. A plurality of two-input gate elements each having a plurality of input signals applied to one input and a plurality of control signals applied to the other input, and an output of the plurality of two-input gate elements. A multi-input gate element, and selecting any one of the plurality of input signals from the output of the multi-input gate element according to the control signal by making any one of the plurality of control signals significant. In the multiplexer for generating the output signal described above, each of the gate elements comprises a polarity reversal gate element that inverts the polarity of the input signal and outputs the inverted signal. 4. A plurality of line changeover switches according to claim 3 are used, each line changeover switch is controlled by a corresponding control signal, and one input is selected and output by each line changeover switch. Thus, the line changeover switch is characterized in that an output signal is generated at a plurality of outputs by selecting from a plurality of input signals. 5. A line switching switch according to claim 4, wherein a redundant switching control signal for performing redundant switching for the plurality of input signals, and a switching for switching between the input signals after the redundant switching. A switching control signal for controlling switching to the line switching switch is generated by taking a logic of a control signal and a redundant switching control signal for performing redundant switching on the line signal after the line switching to generate an output signal. And a line switching control signal generating section, wherein the line switching switch performs redundant switching by collective switching control according to the switching control signal. 6. The line changeover switch according to claim 5, wherein a check code inserting section for inserting a check code having a fixed value into an input signal is provided corresponding to the plurality of input signals, and an output signal is provided. A switching check unit is provided corresponding to each output signal to compare the inserted check code with a predetermined check code to detect an error and check the switching in the line switching switch according to the error. A characteristic line switching check method. 7. The line switching check method according to claim 6, wherein the check code comprises a fixed value inserted in an unused overhead in an overhead byte in the data frame format. 8. The line switching check method according to claim 7, wherein the fixed value comprises the switching control signal. 9. The check code insertion unit prohibits the check code insertion when the input signal is out of frame synchronization or when the input signal is detected to be disconnected. The line switching check method described. 10. The check code inserting section,
7. The line switching check method according to claim 6, wherein AIS is inserted into the input signal and transmitted when frame synchronization cannot be achieved in the input signal or when disconnection of the input signal is detected. 11. The switching check unit prohibits the operation of the switching check when the input signal is out of frame synchronization or when a disconnection of the input signal is detected. Line switching check method. 12. The switching check unit inserts an AIS into an output signal and sends it when the input signal is out of frame synchronization or when a break in the input signal is detected. Line switching check method described in. 13. The switching check unit, when the switching check for the input signal is completed, erases the inserted check code to restore the original fixed data of the overhead byte and outputs the fixed data. Line switching check method described in. 14. In the switching check unit, during the switching check operation, when the frame synchronization cannot be achieved in the input signal or when the disconnection of the input signal is detected, the overhead byte data before the insertion of the check code is converted. 8. The change is prohibited.
Line switching check method described in.