JP2621606B2 - Line switching method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching system, and more particularly to a line switching system for switching a working line and a protection line of a digital wireless communication system at a receiving end.

[Conventional technology]

In a digital wireless communication system having a protection line in addition to a working line, if the transmission quality of the working line deteriorates, the working line and the protection line are connected in parallel at the transmitting end, and the data signal to be transmitted is transmitted in parallel by both lines. Then, the working line is switched to the protection line at the receiving end.

By the way, there is a difference in propagation delay time between the working line and the protection line, and the difference in propagation delay time also varies with time. If the propagation delay time difference is larger than one time slot length of the data signal,
If two data signals are switched as they are at the receiving end, bit duplication or bit omission occurs, and a bit error (hit) occurs.

To avoid this bit error, a hitless line switching method is known in which the receiving end compares the phases of both data signals, corrects the phase difference if it is larger than one time slot length, and then performs line switching. I have.

FIG. 2 is a block diagram showing an example of such a conventional line switching system.

The data signal transmitted on the working line and the data signal transmitted on the protection line are divided into frame synchronization circuits 1a and 1b.
And input to the buffer circuit 3 via the separation circuits 2a and 2b. The buffer circuit 3 is controlled by the line switching control circuit 8 to correct the phase difference by trial and error so that the phase difference between the two input data signals is equal to or less than one time slot. The phase match determination circuit 7 determines whether the phase difference between the two data signals output from the buffer circuit 3 is equal to or less than one time slot. The line switching control circuit 8 causes the buffer circuit 3 to continue trial and error until the determination result becomes a phase match. When the determination result indicates that the phases match, the line switching control circuit 8 switches the switching circuit 4, and the output of the switching circuit 4 switches from the data signal via the working line to the data signal via the protection line.

If the working line is disconnected before the above-described line switching operation is completed, the data signal via the working line becomes meaningless and hitless line switching cannot be performed. In this case, the determination result of the phase matching determination circuit 7 remains in phase mismatch, so that the line switching control circuit 8 forcibly switches the switching circuit 4 after the buffer circuit 3 has taken all possible states through trial and error. Switch.

By the way, in order for the phase match determination circuit 7 to obtain a determination result, a certain time longer than one time stot of the data signal is required. Therefore, the output signal of the voltage controlled oscillator 5 that is phase-synchronized with the clock of the data signal output from the switching circuit 4 is frequency-divided by the frequency divider 6 and the phase match determination circuit 7 Performs the determination operation.

[Problems to be solved by the invention]

The above-described conventional line switching method performs the phase matching determination even when the determination result of the phase matching determination circuit 7 remains in phase mismatch due to disconnection of the working line or the like before the line switching operation is completed. The circuit 7 repeats the determination operation in the cycle of the output signal of the frequency divider 6, changes the states that the buffer circuit 3 can take one by one by trial and error in the cycle of this determination operation, and takes all possible states. Thereafter, since the switching circuit 4 is switched, there is a disadvantage that it takes a long time to switch the line when hitless line switching cannot be performed.

An object of the present invention is to provide a line switching system that can complete line switching in a short time when a working line is deteriorated so that hitless line switching cannot be performed.

[Means for solving the problem]

[Means for Solving the Problems] A line switching system according to the present invention establishes frame synchronization for each of two data signals transmitted through two wireless lines having a redundant relationship with each other, and outputs an alarm signal when frame synchronization is lost. Two frame synchronization circuits that output
The above 2 due to a propagation delay time difference between the two radio lines.
A buffer circuit for variably delaying at least one of the two data signals to correct a phase difference between the two data signals; and a buffer circuit for correcting the phase difference by the buffer circuit. A switching circuit that selects and outputs one of them, a voltage-controlled oscillator that is phase-synchronized with a clock of a data signal output by the switching circuit, a frequency divider that divides the output of the voltage-controlled oscillator, and the frame synchronization circuit. A switch for selecting and outputting an output signal of the voltage-controlled oscillator when the alarm signal is output and selecting and outputting an output signal of the frequency divider when the alarm signal is not output; The above 2 after correction
A phase match determination circuit that determines whether the phases of the two data signals match with the cycle of the output signal of the switch,
A line for controlling the delay of the buffer circuit by trial and error when the phase match determination circuit determines that the phase does not match, and controlling the selection of the switching circuit when the phase match cannot be performed due to the trial and error and when the phase match is determined. A switching control circuit.

Also, the line switching system of the present invention includes two demultiplexing circuits for separating the additional bits multiplexed into the two data signals, and these demultiplexing circuits are connected to the two frame synchronization circuits and the buffer circuit. May be arranged between them.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

The embodiment shown in FIG. 1 is configured by adding a switch 9 to the conventional example shown in FIG.

The switch 9 outputs the output signal of the frequency divider 6 to the phase match determination circuit 7 when neither of the alarm signals Aa and Ab output when the frame synchronization circuits 1a and 1b are out of frame synchronization, and outputs the alarm signal When Aa or Ab is input, the output signal of the voltage controlled oscillator 5 is output to the phase match determination circuit 7.

When the transmission quality of the working line is degraded, the line switching control circuit 8 starts a line switching operation, first sends a switching control signal to a transmitting end (not shown), and makes the working line and the protection line parallel to the transmitting end.

As a result, the data signal to be transmitted is transmitted in parallel to the receiving end on both the working and protection lines. A radio transmission control signal such as a switching control signal and other additional bits are multiplexed on the two data signals transmitted through these two lines,
The frame synchronization bits of the frame for this multiplexing are also multiplexed.

The frame synchronization circuits 1a and 1b detect a frame synchronization bit from each of the two data signals transmitted through the working and protection lines, and establish frame synchronization. The separation circuits 2a and 2b separate additional bits and frame synchronization bits from both transmitted data signals based on the timing of the frame synchronization bits detected by the frame synchronization circuits 1a and 1b, and separate the data signals to be transmitted originally. Output only The frame synchronization circuits 1a and 1b output alarm signals Aa and Ab when the quality of the input data signal is degraded and frame synchronization cannot be established. At this time, the separation circuits 2a and 2b
Separation of additional bits and the like cannot be performed.

When the line switching operation is started and the transmission quality of the working line (and the protection line) is not degraded enough to lose frame synchronization, the alarm signals Aa and Ab are not input to the switch 9 and the phase match determination circuit 7 The output signal of the frequency divider 6 is input to the input terminal.

In this state, the embodiment shown in FIG. 1 operates in the same manner as the conventional example shown in FIG. 2, and performs hitless line switching. That is, in this state, the phase match determination circuit 7
Since the mismatch can be determined normally, and the buffer circuit 3 is configured to be able to always compensate for the propagation delay time difference between the working and protection lines, the buffer circuit 3,
By the trial and error operation performed in the loop of the phase match determination circuit 7 and the line switching control circuit 8, the phases of both data signals output from the buffer circuit 3 match. The line switching control circuit 8 confirms the phase match between the two data signals, and switches the output of the switching circuit 4 from the data signal via the working line to the data signal via the protection line in a hitless manner.

By the way, before the line switching operation is started and completed, the deterioration of the transmission quality of the working line progresses, and when the working line side loses frame synchronization, the alarm signal Aa or Ab is input to the switch 9 and the phase match determination is made. Circuit 7 has a voltage controlled oscillator 5
Output signal is input directly.

In this state, there are many transmission errors in the data signal via the working line, the determination result of the phase matching determination circuit 7 remains in phase mismatch, and hitless line switching cannot be performed. However, in this case, the cycle at which the phase match determination circuit 7 makes a determination is the cycle of the output signal of the voltage-controlled oscillator 5, and is much shorter than the cycle of the determination performed at the cycle of the output signal of the frequency divider 6. I have. Therefore, the line switching control circuit 8 causes the buffer circuit 3 to take successive states in this short cycle,
After taking all possible states, the switching circuit 4 is forcibly switched.

When the line switching time when hitless line switching cannot be performed is compared between the embodiment of FIG. 1 and the conventional example of FIG. 2, the line switching time in the embodiment of FIG.
Is reduced to 1 / n of the line switching time in the conventional example of FIG.

〔The invention's effect〕

As described above, according to the present invention, when the frame synchronization is lost, the determination cycle of the phase matching determination circuit is switched from the cycle of the output signal of the frequency divider to the cycle of the output signal of the voltage-controlled oscillator. While the hitless switching function is maintained, there is an effect that the line switching time required when the working line is deteriorated so that the hitless switching cannot be performed can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional line switching system. 1a, 1b: Frame synchronization circuit, 2a, 2b: Separation circuit, 3
... Buffer circuit, 4 switching circuit, 5 voltage-controlled oscillator, 6 frequency divider, 7 phase match determination circuit, 8
Line switching control circuit, 9 switches.

Claims (2)

(57) [Claims] 1. Two frame synchronization circuits for establishing frame synchronization for each of two data signals transmitted through two wireless lines having a redundant relationship with each other and outputting an alarm signal when frame synchronization is lost. A buffer circuit for variably delaying at least one of the two data signals in order to correct a phase difference between the two data signals due to a propagation delay time difference between the two radio lines;
A switching circuit that selects and outputs one of the two data signals after the phase difference is corrected by the buffer circuit, a voltage-controlled oscillator that is phase-synchronized with a clock of the data signal output by the switching circuit, A frequency divider that divides the output of the voltage controlled oscillator; and a frequency divider that selects and outputs the output signal of the voltage controlled oscillator when the frame synchronization circuit outputs the alarm signal, and outputs the divided signal when the alarm signal is not output. A switch for selecting and outputting an output signal of the frequency divider, and a phase match determination for determining whether or not the phases of the two data signals after correcting the phase difference match with a cycle of the output signal of the switch. The circuit and the phase matching determination circuit determine the phase mismatch by controlling the delay of the buffer circuit by trial and error, and when the phase cannot be matched by the trial and error. Line switching method is characterized in that a circuit switching control circuit for controlling the selection of the switching circuit when it is determined that the phase match. 2. The apparatus according to claim 1, further comprising two demultiplexing circuits for splitting additional bits multiplexed into said two data signals, wherein said demultiplexing circuits are arranged between said two frame synchronization circuits and said buffer circuit. The line switching system according to claim 1, wherein: