JP3076456B2 - Synchronous control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous control system, and more particularly to a synchronous control system for performing synchronization so that cells of a duplex system can be switched without an instantaneous interruption.

2. Description of the Related Art In various communications, a transmission line and a transmission device have a duplex configuration to improve the reliability of a communication network. In the ATM (Asynchronous Transfer Mode) system, digital audio signals, digital image signals,
Various types of data, etc. are fixed-length packets and transmitted as cells.If a duplex configuration is used for the active system and the standby system, when switching is performed, there is no loss or duplication of valid cells. There is a demand for enabling uninterrupted duplex switching.

[0003]

2. Description of the Related Art In a duplex system, for example, as shown in FIG. 10, on a transmission side 31, transmission data is distributed to transmission units 34 and 35 by a distribution unit 33, and transmission units 34 and 3 are transmitted.
5 to the transmission lines 38 and 39, respectively.
On the receiving side 32, the data is received by the receiving units 36 and 37, respectively, and one of the received data is selected and output by the selector 41. That is, as indicated by the two-dot chain line,
The transmission unit 34, the transmission path 38, and the reception unit 36 constitute a system 0 (first system) as an active transmission system.
The transmission path 39 and the receiving unit 37 constitute one system (second system) as a standby transmission system.

In such a duplex system, the AT
A cell according to the M system is transmitted from the transmission side 31 to the reception side 32 and is switched by the 1-system selector 41 when a 0-system failure occurs.

[0005] In this case, as a method of switching without instantaneous interruption, a trigger cell for switching is inserted from the distribution center 33 (not shown) of the transmission side 31 from the center (not shown) side of the network and transmitted to both the system 1 and the system 0. Receivers 36 and 3 of receiver 32
When the switching trigger cells are simultaneously read out from the buffer 7 (not shown), it is determined that the cells of the 0-system and the 1-system are synchronized, and the switching of the selector 41 is controlled. That is, when the selector 41 is controlled to switch between the 0-system and the 1-system, the cell synchronization between the 0-system and the 1-system is established.

[0006] For the cells of system 0 and system 1, the receiving unit 3
6, 37 buffers (not shown) and transmission lines 38, 3
A method is also conceivable in which the transmission delay difference due to 9 or the like is absorbed, the synchronization state is always maintained, and when switching to the 1 system due to the occurrence of a failure in the 0 system or the like, the selector 41 is immediately controlled to perform instantaneous switching.

[0007]

In the synchronous control system using the conventional switching trigger cell as described above, the receiving side 32
Since the switching is performed by the selector 41 when the switching trigger cells are simultaneously read from the buffers of the receiving units 36 and 37, it takes time until the switching trigger cells can be simultaneously detected. In addition, since the switching operation is performed every time the switching trigger cell is simultaneously detected, an empty cell is output from the buffer of the system in which the switching trigger cell has arrived first, while the system in which the switching trigger cell has arrived later. Valid cells are continuously output from the buffer of each of these, and every time switching is performed between these two systems, a phase difference absorption fluctuation occurs,
There is a problem that the density difference of effective cells occurs.

Further, the system in which the buffers in the receiving units 36 and 37 are always in a synchronized state and the selector 41 performs the instantaneous interruption switching is performed after the synchronization is once established by discarding cells or inserting extra cells. There is a disadvantage that synchronization is lost. If such synchronization is lost, when the selector 41 is immediately controlled when switching from the 0 system to the 1 system,
There is a disadvantage that cells are lost or duplicated.

Accordingly, the present invention provides a method for establishing synchronization in a short period of time without generating phase difference absorption fluctuation and controlling the synchronization so as to maintain the synchronization even after cell discarding or extra cell insertion. The purpose is to provide.

[0010]

In order to achieve the above object, a synchronous control system according to the present invention employs, as shown in FIG. 1 (1), an effective control of a first system and a second system in a duplex configuration. First-in first-out (FIFO) memory buffers 1 and 2 for inputting cells and absorbing a phase difference, and a synchronization control unit 3 for controlling the buffers 1 and 2 are provided. The valid cells are read out from the buffers 1 and 2 in synchronism with each other and supplied to the selector 4.
And the second system are switched without any instantaneous interruption.

Each of the systems is provided with synchronous cell detectors 5 and 6, and when one of the synchronous cell detectors 5 and 6 of either system detects a synchronous cell for establishing synchronization inserted into both systems on the transmitting side, The synchronization control unit 3 stops reading of the buffers 1 and 2 of the detected system and determines that synchronization has been established when a synchronization cell of the subsequent system is detected, and the synchronization control unit 3 further performs the synchronization. After the establishment determination, when there is no valid cell in the second or first system buffer while the valid cell can be read from the first or second system buffer, the first or second system The reading of the buffer of the system is stopped, an empty cell is sent out from the first system and the second system, and when a valid cell is input to the buffer of the second or first system, the first and second cells are read. 2 and reads out the valid cell from the buffer of the system
It is characterized by maintaining synchronization.

Further, according to the present invention, the synchronization control unit 3 includes the first
When the synchronous cell is detected in the second system after the synchronous cell is detected in the second system and is not detected even after exceeding the threshold value of the buffer, the reading of the first system is resumed assuming that the synchronous cell has disappeared. be able to.

Further, in the present invention, the synchronization cell may be periodically inserted on the transmission side.

Further, in the present invention, as shown by a dotted line in FIG.
After the synchronization is established, all the valid cells in both systems may be compared with each other to detect a mismatch, thereby detecting loss of synchronization and performing the synchronization establishment determination again.

Further, in the present invention, the cell coincidence comparing circuit 7
However, it is possible to perform cell match comparison by setting a predetermined number of stages of forward protection.

Further, in the present invention, when the effective cell of the first or second system is discarded, the synchronization control unit 3 inserts a dummy cell at a position of the discarded effective cell, and uses the dummy cell as an effective cell to set the buffer in the buffer. , In which case
When the discarded valid cell is determined to be the synchronization cell, it may not be allowed to enter the synchronization establishment determination operation.

[0017]

According to the present invention, first, synchronization is established.
A synchronization cell is inserted into a cell sequence to be transmitted on the transmitting side, and distributed and transmitted to the first system and the second system.

In each of the first and second systems, as shown in the time chart of FIG. 2B, the receiving side of the first system and the second system for some reason have the synchronous cell of the first system for some reason. Assuming that the synchronous cell arrives earlier, the synchronization control unit 3 performs free reading of the cell from the buffer 1 until the synchronous cell arrives (step S1). The detection unit 5 constantly monitors whether or not a synchronous cell is detected (step S2). When a synchronous cell is detected, cell reading from the buffer 1 of the first system is stopped (step S3), and the second cell is read. Wait for the arrival of the synchronous cell of the system.

Thereafter, it is learned that the synchronous cell of the second system that has arrived has been detected by the synchronous cell detector 6 (step S).
4) The synchronization control unit 3 assumes that synchronization has been established (step S5), and the selector 4 can be selected from this time as shown in FIG. 1 (2).

When synchronization is established in this way,
After that, if the ideal state without cell discard and insertion continues,
As shown in (1), the synchronization establishment state continues, but if nothing is done after the synchronization is established, synchronization loss due to cell discarding or insertion occurs until the next synchronization cell as before (see FIG. 2)), a phase difference absorption fluctuation occurs every time a synchronous cell is detected.

Therefore, after this synchronization is established, the synchronization control unit 3
Performs synchronous reading from the buffers 1 and 2 (step S
5).

This synchronous reading will be described with reference to the flowchart of FIG. 4. The synchronous control unit 3 determines whether the first and second buffers (FIFO) 1 and 2 are empty or not. (Steps S11 and S12). If the buffers 1 and 2 are not empty, that is, if valid cells are accumulated, the valid cells of both systems are read out synchronously (step S13).

If the buffer 1 of the first system is empty due to transmission delay or the like, the reading of the buffer 2 of the second system is stopped (step S14), and an empty cell is transmitted from the buffer 2 of the second system. (Step S15). If the buffer 1 is not empty but the buffer 2 is empty, the reading of the buffer 1 is stopped (step S16), and the buffer 1 is read.
More empty cells are transmitted (step S17).

As described above, when there is no valid cell in one buffer due to a transmission delay or the like, when valid cells are read from the other buffer, a shift occurs between the valid cells in both systems. Since the effective cells of the buffer 1 and the effective cells of the buffer 2 are read out synchronously, once synchronization is established, even if there is a variation such as a transmission delay, as shown in FIG. The synchronous state is maintained, the selector 4 is controlled by the system selection control signal, and the first
When switching between the second system and the second system, instantaneous interruption switching can be performed.

According to the present invention, if the synchronization control unit 3 does not detect a synchronization cell in the second system any time after detecting the synchronization cell in the first system, the buffer 1 becomes full and cell discarding occurs. Since this occurs (see FIG. 3 (3)), the synchronization control unit 3 sets a threshold value for each of the buffers 1 and 2, and even if the synchronization cell exceeds the threshold value of the buffer 2 in the second system, it is detected. If not (step S6 in FIG. 2), it is determined that the synchronous cell has been lost (step S7).
The reading of the buffer 1 of the first system is restarted (steps S8 and S9: FIG. 3 (3)).

Although at least one synchronous cell is required in the above, if the synchronous cell is not inserted on the transmitting side thereafter, a request for re-establishment of synchronization such as an initial state or loss of synchronization is made on the receiving side. In the case where occurs, a control may be considered in which a synchronization cell request signal is transmitted from the reception side to the transmission side, and a synchronization cell is inserted in response to the request. In this case, another communication is required between transmission and reception.

Therefore, in the present invention, by periodically inserting the synchronization cell on the transmission side, synchronization establishment and system switching on the reception side become independent of the transmission side, and both transmission and reception can be easily controlled. it can.

Further, if the number of cells in both systems is different for some reason after the synchronization is established by the synchronization cell, the phase synchronization is lost. However, in the method in which only the synchronous cell is monitored as described above, this loss of synchronization cannot be detected until the next synchronous cell arrives, and when switching is performed at this time, cell duplication or loss occurs, and instantaneous Disconnection switching cannot be guaranteed.

Therefore, according to the present invention, as shown by the dotted line in FIG. 1A, a cell match comparison circuit 7 is provided at the preceding stage of the selector 4 to compare the numbers of all valid cells of both systems after the synchronization is established. By detecting the mismatch, preferably by a predetermined number of stages of forward protection, the out-of-synchronization is detected, and at this time, the synchronization establishing operation can be performed again.

In the above description, the cell may be discarded due to a bit error in the header of the cell or the like. Since the discarded cell is an empty cell, it is not stored in the buffer. Therefore, when a cell is discarded, even if valid cells are read out from the buffers 1 and 2 synchronously, only cells having different contents are read out at the same time, resulting in a state different from the actual synchronization state.

Therefore, in the present invention, a dummy cell is inserted instead of a discarded cell, and the dummy cell is input to the buffer as a valid cell. As a result, the contents of the valid cells after the dummy cell become the same, and the actual synchronized state can be maintained.

However, in this case, if the discarded valid cell happens to be a synchronization cell, the synchronization control unit 3 enters the synchronization establishment determination operation as described above even though phase synchronization has been established, and In this case, a dummy cell is inserted in place of a discarded cell. In this case, after synchronization is established, the synchronization cell is regarded as a normal cell. It may not be allowed to enter the synchronization establishment determination operation.

[0033]

5 to 7 are time charts showing the operation of the synchronous control system according to the present invention shown in FIGS. 1 to 4, particularly the operation of FIGS. 2 and 4. In FIG. Are buffers 0 (FIFO) of systems 0 and 1 respectively corresponding to the first system and the second system shown in FIG. 1, and Y, Z, A, B, C,.
Indicates a valid cell, and a dotted line indicates an empty cell. Among them, FIG. 5 shows the operation of the embodiment for establishing the synchronization using the synchronization cell (phase cell) B, and FIGS. 6 and 7 show the operation of the embodiment for maintaining the synchronization after the establishment of the synchronization. ing.

First, in FIG. 5, (A1) indicates that the 0 system and 1
This shows a state in which the valid cells Y are input to the buffer 1 while the buffers 1 and 2 with the system are empty, and the valid cells Y are input to the buffer 2 with a delay of three cells. Also, (A2)
, A valid cell Y is read from the buffer 1 of the system 0, an empty cell is sent to the system 1 for the valid cell Y, and the valid cell Z is accumulated in the buffer 1 and is waiting for the next reading. Indicates the status.

(A3) shows a state in which a synchronization cell B for establishing synchronization is accumulated in the buffer 1 and a valid cell Y is accumulated in the buffer 2, and the synchronization cell B for establishing synchronization is the buffer 1 of the 0 system. , A synchronization control unit (not shown) detects a synchronization cell B for establishing synchronization,
Until the synchronization cell B is stored in the buffer 0, the reading of the buffer 1 of the system 0 is stopped and an empty cell is sent to the system 0. In this case, 1
Since the buffer 2 of the system is in an empty state, an empty cell is transmitted to the system 1.

Accordingly, the state of (A4) in FIG.
When the state shifts to the state 5) and the synchronization cells B for establishing synchronization are accumulated in the buffers 1 and 2 as shown in (A5), the stop of reading from the 0-system buffer 1 is released, and the buffers 1 and 2 are released. , The synchronization cell B is read out in synchronization with the state shown in FIG. 6 (A6), and synchronization is established.

After the synchronization is established in this way, FIG.
For example, as shown in (A7) of FIG.
If the valid cells D, E, F, and G of the system are delayed from the system 0 and the buffer 2 of the system 1 becomes empty, the reading of the buffer 1 of the system 0 is stopped, and empty cells are sent to both systems. Therefore, 0
In the system buffer 1, valid cells D, E, and F are stored.

Next, as shown in (A8), when the valid cells D of the first system are accumulated in the buffer 2, the reading stop is released, and the valid cells D are synchronized in a manner as shown in (A9). Is read. Therefore, synchronization is maintained even in the state (A10).

In the same manner as described above, (A11) in FIG.
In (A14), since the buffer 2 of the system 1 becomes empty, the reading of the buffer 1 of the system 0 is stopped, and when a valid cell is input to the buffer 2 of the system 1, the buffers 1 and 2 of the systems 2 Reading can be performed and synchronization can be maintained.

FIG. 8 is a diagram for explaining a case where a problem of cell discard occurs in the above embodiment of the present invention, and (B1)
As shown in the figure, for example, a case where the effective cell G of the first system is discarded is shown. Therefore, as shown in (B2), valid cells F are accumulated at the head of buffers 1 and 2 of system 0 and system 1, and the valid cells F are read out synchronously as shown in (B3). Thereafter, the valid cells G are accumulated at the head of the buffer 1 of the system 0, but the valid cells G are not input to the buffer 2 of the system 1;
Since the reading of the buffer 1 of the system is stopped, the synchronization control unit 3 sends an empty cell to both systems as shown in (B4).

Next, as shown in (B5), when the effective cells H are accumulated in the first system buffer 2, as shown in (B6), the valid cells G are transferred from the 0 system buffer 1 to the first system buffer 2. The valid cells H are simultaneously read from the buffer 2 and sent out, and the state is out of phase synchronization. This state is (B7)
It will continue thereafter. That is, when no cell is discarded, the synchronization can be maintained by the above-described embodiment, but when the cell is discarded, the phase is out of phase.

Therefore, in the present invention, as shown in FIG.
Cell X is a dummy cell instead of cell G discarded,
This is input to the buffer as a valid cell.
That is, as shown in (B1) and (B2) of FIG. 8, when the valid cell G is discarded, in this embodiment, as shown in (C1) of FIG. And For example, if the cell is discarded due to a bit error in the header of the cell, the header is modified so that it can be handled as a valid cell.

After the dummy cell X is placed after the valid cell F,
As shown in (C2), the data is input to the buffer 2 of the first system,
As shown in (C3), a valid cell G is stored at the head of the buffer 1 and a dummy cell X is stored at the head of the buffer 2, and as shown in (C4), the valid cell G and the dummy cell X are simultaneously read. Then, as shown in (C5), valid cells H are accumulated at the heads of the buffers 1 and 2, and thereafter, phase synchronization is maintained as shown in (C6) and (C7). become.

It should be noted that the present invention is not limited to the above-described embodiments but can be variously added and changed. The present invention is applied to a duplex system in which data is packetized and transmitted. Can be made possible.

[0045]

As described above, in the synchronization control system according to the present invention, a synchronization cell detecting section is provided in each system, and the synchronization cells for establishing synchronization inserted in both systems on the transmission side are used in either system. When the synchronization is detected, the reading of the buffer of the detected system is stopped, and it is determined that the synchronization has been established when the synchronization cell of the subsequent system is detected. After the synchronization establishment determination, the buffer of the first system becomes empty. In this case, the reading of the buffer of the second system is stopped, and until a valid cell arrives at the first system.
Since the synchronization is maintained by waiting for the valid cell of the second system, the phase difference absorption fluctuation when switching between the first system and the second system is performed except for the first time. Can be eliminated and instantaneous interruption switching can be performed at any time after synchronization is established, so that the time until switching can be reduced.

Even if one of the cells in the system becomes insufficient due to a header error or the like, the synchronization can be maintained by inserting a dummy cell instead and inputting the dummy cell as a valid cell to the buffer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a principle of a receiving side of a synchronous control system according to the present invention.

FIG. 2 is a flowchart illustrating a synchronization establishing process in the synchronization control method according to the present invention.

FIG. 3 is an operation time chart of the synchronous control method according to the present invention.

FIG. 4 is a flowchart illustrating a synchronization maintaining process in the synchronization control method according to the present invention.

FIG. 5 is a time chart of an operation example (synchronization establishment) of the synchronization control method according to the present invention.

FIG. 6 is a time chart of an operation example (maintaining synchronization) of the synchronization control method according to the present invention.

FIG. 7 is a time chart of an operation example (maintaining synchronization) of the synchronization control method according to the present invention.

FIG. 8 is a time chart for explaining a problem of cell discarding in the operation example of the synchronization control method according to the present invention.

FIG. 9 is a time chart of an embodiment in which the problem of cell discard is solved by the synchronization control method according to the present invention.

FIG. 10 is a block diagram showing a conventional dual system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 First system buffer (FIFO) 2 Second system buffer (FIFO) 3 Synchronization control unit 4 Selector 5, 6 Synchronous cell detection unit 7 Cell coincidence comparison unit .

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Nobuyuki Gouchi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hiroshi Ota 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation In-company (72) Inventor Hiromi Ueda 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-5-336157 (JP, A) JP-A-6-62036 (JP) JP-A-5-227191 (JP, A) JP-A-4-222138 (JP, A) JP-A-4-346538 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H04L 12/28 H04L 12/56 H04L 1/22

Claims (7)

(57) [Claims] A first-in / first-out memory buffer (1), (2) for inputting valid cells of a first system and a second system in a duplex configuration and absorbing a phase difference, respectively; A synchronous control unit (3) for controlling 1) and (2),
The synchronization control unit (3) reads out the valid cell from the buffers (1) and (2) in synchronism with each other and supplies it to the selector (4).
(4) In the synchronous control system for switching between the first system and the second system without instantaneous interruption in (4), each system is provided with a synchronous cell detector (5), (6), When the synchronous cell detectors (5) and (6) of the transmitter detect the synchronous cells for establishing synchronization inserted in both systems on the transmitting side, the synchronous controller
In (3), the reading of the buffers (1) and (2) of the detected system is stopped, and it is determined that the synchronization has been established when the synchronization cell of the subsequent system is detected. After the synchronization establishment determination, the first
Alternatively, when there is no valid cell in the second or first system buffer while valid cells can be read from the second system buffer, the reading of the first or second system buffer is stopped. And sending out empty cells from the first system and the second system,
When a valid cell is input to the buffer of the second or first system, the valid cell is read from the buffers of the first and second systems in synchronization with each other, and the synchronization is maintained. Synchronous control method. 2. When the synchronization control unit (3) detects the synchronization cell in the first system and does not detect the synchronization cell in the second system exceeding the threshold of the buffer, the synchronization control unit (3) performs the synchronization. 2. The synchronization control method according to claim 1, wherein reading of the first system is resumed assuming that the cell has disappeared. 3. The synchronization control method according to claim 1, wherein the synchronization cells are periodically inserted on a transmission side. 4. A cell match comparison circuit (7) is provided in a stage preceding the selector (4), and all valid cells of both systems after the establishment of the synchronization are compared to detect a mismatch, thereby detecting a loss of synchronization. 4. The synchronization control method according to claim 1, wherein the synchronization establishment determination is performed again. 5. The synchronization control method according to claim 4, wherein said cell coincidence comparing circuit sets a predetermined number of stages of forward protection and performs cell coincidence comparison. 6. The synchronization control unit (3) inserts a dummy cell at the position of the discarded valid cell when discarding the valid cell of the first or second system, and makes the dummy cell a valid cell in the buffer. The synchronization control method according to claim 1, wherein an input is made. 7. The synchronization control unit according to claim 1, wherein when the synchronization control unit determines that the discarded valid cell is the synchronization cell, the synchronization control unit does not enter the synchronization establishment determination operation. The synchronous control method described in Crab.