JPS6118235A - Synchronizing system in digital communication system - Google Patents

Synchronizing system in digital communication system

Info

Publication number
JPS6118235A
JPS6118235A JP13854484A JP13854484A JPS6118235A JP S6118235 A JPS6118235 A JP S6118235A JP 13854484 A JP13854484 A JP 13854484A JP 13854484 A JP13854484 A JP 13854484A JP S6118235 A JPS6118235 A JP S6118235A
Authority
JP
Japan
Prior art keywords
frame
synchronization
signal
circuit
synchronism
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13854484A
Other languages
Japanese (ja)
Inventor
Masato Tamura
真人 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13854484A priority Critical patent/JPS6118235A/en
Publication of JPS6118235A publication Critical patent/JPS6118235A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To prevent out of synchronism at each multi-frame by unlocking the synchronization at each frame and then locking the synchronization when the state not synchronized at each multi-frame is consecutive for a prescribed time after the synchronization is established at each frame. CONSTITUTION:A frame synchronizing circuit 11 takes synchronism with a reception digital signal PCMR at each frame based on a reception signal CLKR, outputs a frame signal SFR, which is fed to a multi-frame synchronizing circuit 12. The circuit 12 is activated so as to take synchronism with the signal PCMR at each multi-frame. A timing circuit 13 is activated with a signal S1 when the circuit 11 is synchronized and with a signal S2 when the circuit 12 is not synchronized, the time after the synchronization is taken at each frame until the synchronization at each multi-frame is taken is counted, and when this time exceeds a predetermined set time T, a control signal SC is outputted. The circuit 11 receives the signal SC to release the synchronizing state forcibly and the synchronization at each multi-frame is taken by taking synchronism again at each frame.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はＰ　ＣＭ　（Ｐｕｌｓｅ　Ｃｏｄｓ　Ｍｏｄ
ｕｌａｔ　１ｏｎ）通信等のディジタル通信システムの
同期方式に関する。[Detailed description of the invention] [Industrial application field] This invention is based on PCM (Pulse Cods Mod
This invention relates to a synchronization method for digital communication systems such as ULAT 1ON) communication.

〔従来技術〕[Prior art]

ＰＣＭ通信においては、複数のチャネル（例えば、３０
チヤネル）によって１フレームを構成し、さらに複数の
フレーム（例えば、１６フレーム）によってマルチフレ
ームを構成している。そしてこレラ各フレームおよびマ
ルチフレームから所定の情報を抽出するためには、各フ
レームおよびマルチフレームの境界を判別するための１
フレーム毎の同期およびマルチフレーム毎の同期確立が
必要となる。これらの同期確立は、送信側で各フレーム
の特定箇所に適当な同期パターンを挿入しておき、受信
側において、この同期パターンと受信側で形成した対応
パターンとを比較、照合することによって行われる。In PCM communication, multiple channels (e.g. 30
One frame is composed of one frame (channel), and a multiframe is composed of a plurality of frames (for example, 16 frames). In order to extract predetermined information from each frame and multi-frame, it is necessary to
It is necessary to establish synchronization for each frame and for each multiframe. These synchronizations are established by inserting an appropriate synchronization pattern into a specific part of each frame on the sending side, and then comparing and matching this synchronization pattern with the corresponding pattern formed on the receiving side on the receiving side. .

第２図は、上述の従来の同期方式を示すブロック図であ
る。この図において、フレーム同期回路１は、受信クロ
、り信号ＣＬＫＲを基にして受信ディジタル信号ＰＣＭ
Ｒとフレーム毎の同期をとり、この受信ディジタル信号
ＰＣＭＲ中のフレーム同期信号と位相が対応するフレ−
２ム信号８ＦＲを出力する。前記フレーム信号８ＦＲは
、マルチフレーム同期回路２に供給され、この同期回路
２は、フレーム信号８ＦＲを基にして受信ディジタル信
号ＰＣＭＲとマルチフレーム毎の同期をとるよう動作す
る。FIG. 2 is a block diagram showing the conventional synchronization method described above. In this figure, a frame synchronization circuit 1 converts a received digital signal PCM based on a received black signal CLKR.
Synchronizes frame by frame with R, and synchronizes the frame whose phase corresponds to the frame synchronization signal in the received digital signal PCMR.
2m signal 8FR is output. The frame signal 8FR is supplied to a multiframe synchronization circuit 2, and the synchronization circuit 2 operates to synchronize each multiframe with the received digital signal PCMR based on the frame signal 8FR.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の従来の同期方式においては、フレーム同期が疑似
同期状態に陥ってしまうと、フレーム信号８ＦＨの位置
が正常々同期位置からずれてしまうため、フレーム信号
ＳＦＲを基にしているマルチフレーム同期回路２は目的
とする同期確立を永久に達成できないという問題がある
。In the conventional synchronization method described above, if the frame synchronization falls into a pseudo synchronization state, the position of the frame signal 8FH deviates from the normal synchronization position, so the multi-frame synchronization circuit 2 based on the frame signal SFR The problem is that the desired synchronization cannot be achieved forever.

この発明の目的はこの問題を解決するための同期方式を
提供することにある。The purpose of this invention is to provide a synchronization method to solve this problem.

〔問題点解決のための構成〕[Configuration for solving problems]

上記問題解決のために、この発明は、１フレーム毎の同
期確立の後でマルチフレーム毎の同期が確立できない状
態が予め設定された時間継続したときには％　ｌフレー
ム毎に確立した同期を強制的にはずし、再度ｌフレーム
毎の同期マルチフレーム毎の同期をとることを特徴とす
る。In order to solve the above problem, this invention forcibly establishes the synchronization established for each frame when the state in which synchronization for each multi-frame cannot be established continues for a preset period of time after the synchronization for each frame has been established. The feature is that the synchronization is performed once again for each l-frame and for each multi-frame.

〔実施例〕〔Example〕

次に第１図を参照して本発明の一実施例を説明する。第
１図において、フレーム同期回路１１およびマルチフレ
ーム同期回路１２は、第２図に示した対応する同期回路
ｌおよび２と同一の構成を有している。また、タイミン
グ回路１３は、１フレーム毎の同期がとれてからマルチ
フレーム毎の同期がとれるまでの時間を計時するもので
、フレーム同期回路１１が同期したときの信号Ｓｌとマ
ルチフレーム同期回路１２が同期していないときの信号
Ｓ２とによって動作し、前記時間が予め定めた設定時間
Ｔを超えると制御信号ＳＣを出力する。この制御信号８
Ｃを受けて前記同期回路１１は、自身の同期状態を強制
的に解除する。すなわち、１フレーム毎の同期確立後、
設定時間Ｔ経過してもマルチフレーム毎の同期が確立で
きないときには、１フレーム毎の同期を強制的に解除し
、再度、１フレーム毎の同期とマルチフレーム毎の同期
をとるような方式となっている。なお、前記設定時間Ｔ
はマルチフレーム毎の同期復帰時間に基づいて、例えば
、２ｍ８程度に設定される。Next, an embodiment of the present invention will be described with reference to FIG. In FIG. 1, a frame synchronization circuit 11 and a multiframe synchronization circuit 12 have the same configuration as the corresponding synchronization circuits 1 and 2 shown in FIG. Further, the timing circuit 13 measures the time from when synchronization is achieved for each frame until synchronization is achieved for each multi-frame, and the signal Sl when the frame synchronization circuit 11 is synchronized and the multi-frame synchronization circuit 12 are It operates based on the signal S2 when not synchronized, and outputs the control signal SC when the time exceeds a predetermined set time T. This control signal 8
In response to C, the synchronization circuit 11 forcibly cancels its own synchronization state. In other words, after establishing synchronization for each frame,
If multi-frame synchronization cannot be established even after the set time T has elapsed, the system forcibly cancels the frame-by-frame synchronization and re-establishes frame-by-frame synchronization and multi-frame synchronization. There is. Note that the set time T
is set, for example, to about 2m8 based on the synchronization recovery time for each multiframe.

このような構成において、フレーム同期回路１１が正し
い同期状態をとっているときには、タイミング回路１３
の計時が設定時間Ｔ′に至る前にマルチフレーム毎の同
期がとられ、タイミング回路１３がリセットされて同期
状態を継続する。In such a configuration, when the frame synchronization circuit 11 is in a correct synchronization state, the timing circuit 13
Before the time measurement reaches the set time T', synchronization is established for each multi-frame, and the timing circuit 13 is reset to continue the synchronized state.

一方、フレーム同期回路１１が疑似フレーム同期信号に
疑似同期してしまったときには、設定時間Ｔ内にマルチ
フレーム同期かとれず、タイミング回路１３から制御信
号ＳＣが出力され、これによりフレーム同期回路１１の
前記疑似フレーム同期信号との同期関係が強制的に解除
され、再度、１７Ｌ’−ム毎の同期とマルチフレーム毎
の同期がとられる。On the other hand, when the frame synchronization circuit 11 is pseudo-synchronized with the pseudo frame synchronization signal, multi-frame synchronization cannot be achieved within the set time T, and the timing circuit 13 outputs the control signal SC. The synchronization relationship with the pseudo frame synchronization signal is forcibly canceled, and synchronization for each 17L'-frame and for each multiframe is established again.

従って、従来方式において生じるマルチフレーム同期は
ずれという事態を回避できる。Therefore, the situation of multi-frame synchronization that occurs in the conventional method can be avoided.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明には、従来方式において
指摘されるマルチフレーム同期性ずれの問題を解決でき
る。この結果、通信回線効率の著しい改善を達成できる
。As explained above, the present invention can solve the problem of multi-frame synchronization deviation that is pointed out in the conventional system. As a result, a significant improvement in communication line efficiency can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示すブロック図および第２
図は従来方式を示す図である。 １．１１・・・・・・フレーム同期回路。２，１２・・
・・・・マルチフレーム同期回路、１３・・・・・・タ
イミング回路。FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure shows a conventional method. 1.11... Frame synchronization circuit. 2,12...
...Multi-frame synchronization circuit, 13...Timing circuit.

Claims (1)

【特許請求の範囲】[Claims] 受信ディジタル信号と１フレーム毎の同期確立を行なう
第１の同期回路と前記信号と複数フレーム毎の同期確立
を行なう第２の同期回路とを有する同期式ディジタル通
信方式において、前記第１の同期回路と前記受信ディジ
タル信号の同期確立後に前記第２の同期回路と前記受信
ディジタル信号との非同期状態が予め設定された時間継
続したときには前記第１の同期回路と前記受信ディジタ
ル信号との間に確立している同期関係を強制的に解除し
１フレーム毎の同期と複数フレーム毎の同期を再度行な
うようにしたことを特徴とするディジタル通信方式にお
ける同期方式。In a synchronous digital communication system, the first synchronization circuit includes a first synchronization circuit that establishes synchronization with a received digital signal for each frame, and a second synchronization circuit that establishes synchronization with the signal for each of a plurality of frames. When an asynchronous state between the second synchronization circuit and the received digital signal continues for a preset time after synchronization is established between the first synchronization circuit and the received digital signal, the synchronization between the first synchronization circuit and the received digital signal is established. 1. A synchronization method in a digital communication system, characterized in that a synchronization relationship is forcibly canceled, and synchronization for each frame and synchronization for each plurality of frames is performed again.
JP13854484A 1984-07-04 1984-07-04 Synchronizing system in digital communication system Pending JPS6118235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13854484A JPS6118235A (en) 1984-07-04 1984-07-04 Synchronizing system in digital communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13854484A JPS6118235A (en) 1984-07-04 1984-07-04 Synchronizing system in digital communication system

Publications (1)

Publication Number Publication Date
JPS6118235A true JPS6118235A (en) 1986-01-27

Family

ID=15224630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13854484A Pending JPS6118235A (en) 1984-07-04 1984-07-04 Synchronizing system in digital communication system

Country Status (1)

Country Link
JP (1) JPS6118235A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62235697A (en) * 1987-02-10 1987-10-15 三洋電機株式会社 Trouble detection of vending machine
JPS6473833A (en) * 1987-09-14 1989-03-20 Nec Corp Synchronization establishing method
JPH0222942A (en) * 1988-07-12 1990-01-25 Nec Corp Digital transmission system
US9519487B2 (en) 2013-03-14 2016-12-13 Samsung Electronics Co., Ltd. System-on-chip and method of operating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62235697A (en) * 1987-02-10 1987-10-15 三洋電機株式会社 Trouble detection of vending machine
JPS6473833A (en) * 1987-09-14 1989-03-20 Nec Corp Synchronization establishing method
JPH0222942A (en) * 1988-07-12 1990-01-25 Nec Corp Digital transmission system
US9519487B2 (en) 2013-03-14 2016-12-13 Samsung Electronics Co., Ltd. System-on-chip and method of operating the same

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