JPS5454011A - Magnetic memory control device - Google Patents

Magnetic memory control device

Info

Publication number
JPS5454011A
JPS5454011A JP12009277A JP12009277A JPS5454011A JP S5454011 A JPS5454011 A JP S5454011A JP 12009277 A JP12009277 A JP 12009277A JP 12009277 A JP12009277 A JP 12009277A JP S5454011 A JPS5454011 A JP S5454011A
Authority
JP
Japan
Prior art keywords
signals
writing
circuit
response
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12009277A
Other languages
Japanese (ja)
Inventor
Toshihiko Matsuda
Kazuya Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12009277A priority Critical patent/JPS5454011A/en
Publication of JPS5454011A publication Critical patent/JPS5454011A/en
Pending legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To prevent block information other than that designated from being broken by inhibiting the production of the writing allowing signals in response to the time-over signals which are generated by such a time monitoring circuit as is reset upon every writing operation of one word.
CONSTITUTION: In response to writing command signals from a processing device, the reading/writing control circuit 3 of a control station 1 generates write signals so that the output of a NOR gate 9 becomes the writing allowing signals. At the same time, a time monitoring circuit 7, which is released from its reset condition in response to the write signals, and a bit counter 4 count the writing clocks generated by a timing circuit 2 so that the circuit 7 is reset in response to information transfer signals REQ which are generated upon the counting operation of one word of the counter 4. In case there is no signals REQ generated from the counter 4 due to a disorder, the circuit 7 becomes overoutned to generate time-over signals, an FF 8 is set so invert the output of the gate 9 so that the writing operation is prohibited. As a result, the record at a portion other than the designated block can be prevent from being broken due to runaway
COPYRIGHT: (C)1979,JPO&Japio
JP12009277A 1977-10-07 1977-10-07 Magnetic memory control device Pending JPS5454011A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12009277A JPS5454011A (en) 1977-10-07 1977-10-07 Magnetic memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12009277A JPS5454011A (en) 1977-10-07 1977-10-07 Magnetic memory control device

Publications (1)

Publication Number Publication Date
JPS5454011A true JPS5454011A (en) 1979-04-27

Family

ID=14777700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12009277A Pending JPS5454011A (en) 1977-10-07 1977-10-07 Magnetic memory control device

Country Status (1)

Country Link
JP (1) JPS5454011A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165911A (en) * 1980-05-22 1981-12-19 Fujitsu Ltd Data protecting system in magnetic recorder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56165911A (en) * 1980-05-22 1981-12-19 Fujitsu Ltd Data protecting system in magnetic recorder
JPH0235385B2 (en) * 1980-05-22 1990-08-09 Fujitsu Ltd

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