JPS563496A - Memory control circuit - Google Patents

Memory control circuit

Info

Publication number
JPS563496A
JPS563496A JP7572179A JP7572179A JPS563496A JP S563496 A JPS563496 A JP S563496A JP 7572179 A JP7572179 A JP 7572179A JP 7572179 A JP7572179 A JP 7572179A JP S563496 A JPS563496 A JP S563496A
Authority
JP
Japan
Prior art keywords
refresh
action
given
request
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7572179A
Other languages
Japanese (ja)
Inventor
Tadashi Miyazaki
Toshitaka Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7572179A priority Critical patent/JPS563496A/en
Publication of JPS563496A publication Critical patent/JPS563496A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To avoid the effect to be given to the CPU process time by the refresh action excepting the case both the actions occur at one time, by giving the priority to the refresh and write/read actions of the memory based on the occurring order and then giving the queuing to the other action having the request later. CONSTITUTION:FF1 is set according to the writing and reading request given from the CPU, and thus the writing and reading is permitted for the RAM. And the refresh action is permitted via FF2 which is set according to the refresh request. At the same time, FF1, FF3 are set and reset each by FF2. And the priority is given to the refresh action in case the refresh request is given first. Thus the writing and reading action having the request later is made to queue until the end of the refresh action via the queuing signal produced by the set output of FF3. As a result, the CPU is never set under the queuing state at the refresh action time excepting the case both the refresh and write/read actions occur at one time. Thus no effect is given to the CPU process time by the refresh action.
JP7572179A 1979-06-18 1979-06-18 Memory control circuit Pending JPS563496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7572179A JPS563496A (en) 1979-06-18 1979-06-18 Memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7572179A JPS563496A (en) 1979-06-18 1979-06-18 Memory control circuit

Publications (1)

Publication Number Publication Date
JPS563496A true JPS563496A (en) 1981-01-14

Family

ID=13584403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7572179A Pending JPS563496A (en) 1979-06-18 1979-06-18 Memory control circuit

Country Status (1)

Country Link
JP (1) JPS563496A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212691A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Memory refreshment control system
JPS5826394A (en) * 1981-08-06 1983-02-16 Fujitsu Ltd Competition circuit
JPS59186059A (en) * 1983-04-08 1984-10-22 Hitachi Micro Comput Eng Ltd Circuit for prevent competition
EP0237785A2 (en) * 1986-02-14 1987-09-23 Kabushiki Kaisha Toshiba Dynamic read/write memory with improved refreshing operation
JPS63222391A (en) * 1987-03-11 1988-09-16 Nec Corp Refresh control system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57212691A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Memory refreshment control system
JPS5826394A (en) * 1981-08-06 1983-02-16 Fujitsu Ltd Competition circuit
JPS59186059A (en) * 1983-04-08 1984-10-22 Hitachi Micro Comput Eng Ltd Circuit for prevent competition
EP0237785A2 (en) * 1986-02-14 1987-09-23 Kabushiki Kaisha Toshiba Dynamic read/write memory with improved refreshing operation
JPS63222391A (en) * 1987-03-11 1988-09-16 Nec Corp Refresh control system

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