JPS55118292A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS55118292A
JPS55118292A JP2530479A JP2530479A JPS55118292A JP S55118292 A JPS55118292 A JP S55118292A JP 2530479 A JP2530479 A JP 2530479A JP 2530479 A JP2530479 A JP 2530479A JP S55118292 A JPS55118292 A JP S55118292A
Authority
JP
Japan
Prior art keywords
input information
memory address
unit
line
line number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2530479A
Other languages
Japanese (ja)
Inventor
Teruo Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2530479A priority Critical patent/JPS55118292A/en
Publication of JPS55118292A publication Critical patent/JPS55118292A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To realize the processing system that the input information from the line is tentatively stored, each transaction memory address relating based on the line number of the input information in reading out it is produced, and it is stored in the specific area of the main memory unit. CONSTITUTION:The central processing unit 1 reads out the input information from the line by means of the waiting queue circuit 5 with the program stored in the main memory unit 2. In this case, the line number information is inputted to the transaction memory address production circuit 6, which produces the transaction memory address from the line number with the start signal and writes in the transaction memory address to the specific area of the main memory unit 2. Thus, the overhead in input information unit can be reduced to increase the processing ability.
JP2530479A 1979-03-05 1979-03-05 Data processing system Pending JPS55118292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2530479A JPS55118292A (en) 1979-03-05 1979-03-05 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2530479A JPS55118292A (en) 1979-03-05 1979-03-05 Data processing system

Publications (1)

Publication Number Publication Date
JPS55118292A true JPS55118292A (en) 1980-09-11

Family

ID=12162266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2530479A Pending JPS55118292A (en) 1979-03-05 1979-03-05 Data processing system

Country Status (1)

Country Link
JP (1) JPS55118292A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138651A (en) * 1983-12-27 1985-07-23 Fujitsu Ltd Buffer memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138651A (en) * 1983-12-27 1985-07-23 Fujitsu Ltd Buffer memory

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