JPS5727328A - Control device - Google Patents

Control device

Info

Publication number
JPS5727328A
JPS5727328A JP10278780A JP10278780A JPS5727328A JP S5727328 A JPS5727328 A JP S5727328A JP 10278780 A JP10278780 A JP 10278780A JP 10278780 A JP10278780 A JP 10278780A JP S5727328 A JPS5727328 A JP S5727328A
Authority
JP
Japan
Prior art keywords
information
terminal
inputted
signal
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10278780A
Other languages
Japanese (ja)
Inventor
Toshinori Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10278780A priority Critical patent/JPS5727328A/en
Publication of JPS5727328A publication Critical patent/JPS5727328A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To permit connection to processors of both types of common and separating buses by storing information in an address latch at the inputting of a selection signal, storing data information in a register at the inputting of a write instruction signal and storing the information onto one of them when both signals input. CONSTITUTION:A terminal 5 to be inputted with a selection signal SS selecting an address latch 2, a terminal 6 to be inputted with an instruction signal WS for writing information into a data register group 3, and a terminal 7 to be inputted with information are provided. When the signal SS is inputted from the terminal 5, the information from the terminal 7 is stored as address information into the latch 2, and when the signal WS from the terminal 6 is inputted, the information from the terminal 7 is stored as data information into the selected register. When the signals SS, WS from the terminals 5, 6 are inputted, the information from the terminal 7 is stored as address information into the latch 2. Thereby, the connection to processors of either type of common and separating buses is made possible.
JP10278780A 1980-07-25 1980-07-25 Control device Pending JPS5727328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10278780A JPS5727328A (en) 1980-07-25 1980-07-25 Control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10278780A JPS5727328A (en) 1980-07-25 1980-07-25 Control device

Publications (1)

Publication Number Publication Date
JPS5727328A true JPS5727328A (en) 1982-02-13

Family

ID=14336833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10278780A Pending JPS5727328A (en) 1980-07-25 1980-07-25 Control device

Country Status (1)

Country Link
JP (1) JPS5727328A (en)

Similar Documents

Publication Publication Date Title
JPS5582359A (en) Microprogram test unit
JPS57117027A (en) Signal sending and receiving circuit
ATE55528T1 (en) VIDEO SIGNAL PROCESSING CIRCUITS.
JPS5727328A (en) Control device
JPS57130150A (en) Register control system
JPS57113169A (en) Microcomputer
JPS5510614A (en) Controller
JPS57103547A (en) Bit word access circuit
JPS5510620A (en) Output change-over circuit
JPS6423354A (en) Duplex buffer memory control system
JPS5533282A (en) Buffer control system
JPS573291A (en) Associative memory circuit
JPS5740790A (en) Storage control system
JPS6423488A (en) Memory
JPS55108038A (en) Information renewal system for input monitor memory
JPS57137938A (en) Data processor
JPS5614358A (en) Operation log storing system
JPS5715297A (en) Memory element
JPS5730454A (en) Terminal equipment
JPS55118292A (en) Data processing system
JPS5647194A (en) Time slot allocating circuit
JPS56117393A (en) Rom write-in readout system
JPS57105036A (en) Register means access system
JPS6481031A (en) Data control system
JPS5532263A (en) Check system for write data