JPS5715297A - Memory element - Google Patents
Memory elementInfo
- Publication number
- JPS5715297A JPS5715297A JP8922980A JP8922980A JPS5715297A JP S5715297 A JPS5715297 A JP S5715297A JP 8922980 A JP8922980 A JP 8922980A JP 8922980 A JP8922980 A JP 8922980A JP S5715297 A JPS5715297 A JP S5715297A
- Authority
- JP
- Japan
- Prior art keywords
- data
- address
- gate
- storing
- signal generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To obtain a memory element which is equipped with a peripheral circuit and can be diagnosed easily by automatically generated diagnostic data, by providing a storing circuit which stores an address signal in data reading operation and a specific controlling means. CONSTITUTION:A storing circuit storing an address signal in data reading operation and a controlling means of reading the contents of the storing circuit in data writing operation are provided. For example, an address decoder 1, a write control signal inverting gate 2, a data write clock signal generating AND gate 3, a data read control signal generating AND gate 4, a data storing FF5, and a data read selection AND gate 7 are provided. Further, an address storing FF6, an address read selection AND gate 8, and an address write clock signal generating gate 9 are newly provided, and address signals A and A1 are inputted to the decoder 1 and also supplied to the FF6 as input data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8922980A JPS5715297A (en) | 1980-07-02 | 1980-07-02 | Memory element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8922980A JPS5715297A (en) | 1980-07-02 | 1980-07-02 | Memory element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5715297A true JPS5715297A (en) | 1982-01-26 |
JPS6331880B2 JPS6331880B2 (en) | 1988-06-27 |
Family
ID=13964908
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8922980A Granted JPS5715297A (en) | 1980-07-02 | 1980-07-02 | Memory element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5715297A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62119366A (en) * | 1985-11-18 | 1987-05-30 | ダイキン工業株式会社 | Refrigerator |
-
1980
- 1980-07-02 JP JP8922980A patent/JPS5715297A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62119366A (en) * | 1985-11-18 | 1987-05-30 | ダイキン工業株式会社 | Refrigerator |
Also Published As
Publication number | Publication date |
---|---|
JPS6331880B2 (en) | 1988-06-27 |
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