JPS5654678A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5654678A
JPS5654678A JP12944079A JP12944079A JPS5654678A JP S5654678 A JPS5654678 A JP S5654678A JP 12944079 A JP12944079 A JP 12944079A JP 12944079 A JP12944079 A JP 12944079A JP S5654678 A JPS5654678 A JP S5654678A
Authority
JP
Japan
Prior art keywords
signal
pulse
memory
output
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12944079A
Other languages
Japanese (ja)
Inventor
Hideyoshi Inauchi
Satoshi Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12944079A priority Critical patent/JPS5654678A/en
Publication of JPS5654678A publication Critical patent/JPS5654678A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To secure the working mode for the memory chip only for the time necessary for the working and thus reduce the power comsumption, by turning off immediately the chip selection signal at the moment of completion of the read/write actions of the signal. CONSTITUTION:The chip selection signals CS0-CSn obtained by decoding the address signal (a) are applied to one input of each gate forming the NAND gate array 2. When the memory 1 is read, the reset pulse (g) is produced through the differentiation circuit 6 of the strobe pulse (e) which samples the data (d) to be applied to the reset input of the FF3. Thus the signal CS is obtained at the output of the gate corresponding to the array 2 via the output of the FF3 to be applied to the memory chip of the corresponding line. And when the writing is given to the memory 1, the pulse (g) obtained by differentiation circuit 5 the write pulse (f) is applied to the FF3. Thus the signal CS is obtained at the output of the gate corresponding to the array 2.
JP12944079A 1979-10-09 1979-10-09 Memory control system Pending JPS5654678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12944079A JPS5654678A (en) 1979-10-09 1979-10-09 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12944079A JPS5654678A (en) 1979-10-09 1979-10-09 Memory control system

Publications (1)

Publication Number Publication Date
JPS5654678A true JPS5654678A (en) 1981-05-14

Family

ID=15009512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12944079A Pending JPS5654678A (en) 1979-10-09 1979-10-09 Memory control system

Country Status (1)

Country Link
JP (1) JPS5654678A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200888U (en) * 1987-06-16 1988-12-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200888U (en) * 1987-06-16 1988-12-23

Similar Documents

Publication Publication Date Title
WO1987000675A3 (en) Control system for chained circuit modules
JPS56134390A (en) Rom element
JPS5654678A (en) Memory control system
JPS55134442A (en) Data transfer unit
JPS5616980A (en) Write-in system of one-bit of memory
JPS563496A (en) Memory control circuit
JPS573141A (en) Memory device for pipeline operation
JPS5699550A (en) Information processing unit
JPS53107240A (en) Control system of register memory
JPS57208688A (en) Clock generating system
JPS5737795A (en) Read-only memory element
JPS57189229A (en) Recording and controlling system for career information
SU802959A1 (en) Information sorting device
JPS54123841A (en) Semiconductor integrated memory element
JPS53126823A (en) Writing system for refresh memory
JPS578980A (en) Memory device
JPS6482389A (en) Semiconductor memory
SU765878A1 (en) Long-time memory
JPS54148339A (en) Memory device
JPS6425257A (en) Memory controller
SU1228146A1 (en) Storage for programmed controller
JPS5718085A (en) Rom
SU1425789A1 (en) Device for shaping rapid-access memory test
JPS56105546A (en) Memory mapping circuit
JPS5566042A (en) Memory control circuit