JPS5724093A - Memory cell - Google Patents

Memory cell

Info

Publication number
JPS5724093A
JPS5724093A JP9857780A JP9857780A JPS5724093A JP S5724093 A JPS5724093 A JP S5724093A JP 9857780 A JP9857780 A JP 9857780A JP 9857780 A JP9857780 A JP 9857780A JP S5724093 A JPS5724093 A JP S5724093A
Authority
JP
Japan
Prior art keywords
line
read
write
terminals
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9857780A
Other languages
Japanese (ja)
Inventor
Masao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9857780A priority Critical patent/JPS5724093A/en
Publication of JPS5724093A publication Critical patent/JPS5724093A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To eliminate the change of potential between substata of a cell and increase the line selecting speed, by opening and closing a write/read control FET to carry out a selection of address plus a read/write action. CONSTITUTION:Read/write FET205 and 206 are connected to a writing circuit 215 and a sense amplifier 216 via write/read lines 209 and 210, and each gate is connected to a line address line transistor circuit 217 via a line 214. In the reading mode, a pulse 301 is applied to an address line 114, and read control pulses 304 and 307 are applied to terminals 209 and 210 each. Thus the change of current at the terminals 209 and 210 is detected by an amplifier 216, and the storage contents of a cell is read. While in the writing mode, a line address selection pulse 302 is applied to the line 114, and writing pulses 305 and 308 are applied to the terminals 209 and 210. Thus the potential of a terminal 211 is changed to a low level from a high level. At the same time, an FET202 is turned to eff from on and an FET201 is turned to on from off. Thus ''0'' for instance is written.
JP9857780A 1980-07-18 1980-07-18 Memory cell Pending JPS5724093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9857780A JPS5724093A (en) 1980-07-18 1980-07-18 Memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9857780A JPS5724093A (en) 1980-07-18 1980-07-18 Memory cell

Publications (1)

Publication Number Publication Date
JPS5724093A true JPS5724093A (en) 1982-02-08

Family

ID=14223515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9857780A Pending JPS5724093A (en) 1980-07-18 1980-07-18 Memory cell

Country Status (1)

Country Link
JP (1) JPS5724093A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62254463A (en) * 1986-04-17 1987-11-06 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Static memory cell with bipolar and mos devices
JPH04318395A (en) * 1991-02-13 1992-11-09 Internatl Business Mach Corp <Ibm> Memory cell circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62254463A (en) * 1986-04-17 1987-11-06 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン Static memory cell with bipolar and mos devices
JPH04318395A (en) * 1991-02-13 1992-11-09 Internatl Business Mach Corp <Ibm> Memory cell circuit

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