JPS5447445A - Memory unit - Google Patents
Memory unitInfo
- Publication number
- JPS5447445A JPS5447445A JP11272377A JP11272377A JPS5447445A JP S5447445 A JPS5447445 A JP S5447445A JP 11272377 A JP11272377 A JP 11272377A JP 11272377 A JP11272377 A JP 11272377A JP S5447445 A JPS5447445 A JP S5447445A
- Authority
- JP
- Japan
- Prior art keywords
- bank
- signal
- address
- indication
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To secure a constant access to the memory with no consciousness of the refresh cycle, by dividing the memory into two banks which memorize the same contents and refreshing one bank while the other bank is being read out. CONSTITUTION:The memory is divided into bank 5 and bank 6 which memorize the same contents. When reading is indicated, control circuit 1 selects access address signal 16 to address switch 3 and gives indication 13 to supply the signal to bank 5. At the same time, refresh RF address signal 15 is selected to address switch 4, and indication 12 is given to supply the signal to bank 6, and RF indication signal 9 is turned on to start the RF action of bank 6. Then output switch 7 receives indication 14 to select the output data, and the reading data is delivered to output data bus 18. When writing, the contents of input data bus 17 are written into the same address of the both banks via writing signal 11. (In this cycle, the RF is inhibited for both banks.)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52112723A JPS586232B2 (en) | 1977-09-21 | 1977-09-21 | memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52112723A JPS586232B2 (en) | 1977-09-21 | 1977-09-21 | memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5447445A true JPS5447445A (en) | 1979-04-14 |
JPS586232B2 JPS586232B2 (en) | 1983-02-03 |
Family
ID=14593909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52112723A Expired JPS586232B2 (en) | 1977-09-21 | 1977-09-21 | memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS586232B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004507856A (en) * | 2000-08-17 | 2004-03-11 | マイクロン・テクノロジー・インコーポレーテッド | Method and system for hiding refresh of dynamic random access memory |
KR100429872B1 (en) * | 2001-06-27 | 2004-05-04 | 삼성전자주식회사 | Memory system for promoting efficiency of use of semiconductor memory and refresh method of the semiconductor memory |
JP2012512496A (en) * | 2009-05-25 | 2012-05-31 | ソンゼ イ, | Apparatus and method for implementing SRAM output characteristics in DRAM |
-
1977
- 1977-09-21 JP JP52112723A patent/JPS586232B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004507856A (en) * | 2000-08-17 | 2004-03-11 | マイクロン・テクノロジー・インコーポレーテッド | Method and system for hiding refresh of dynamic random access memory |
KR100429872B1 (en) * | 2001-06-27 | 2004-05-04 | 삼성전자주식회사 | Memory system for promoting efficiency of use of semiconductor memory and refresh method of the semiconductor memory |
JP2012512496A (en) * | 2009-05-25 | 2012-05-31 | ソンゼ イ, | Apparatus and method for implementing SRAM output characteristics in DRAM |
Also Published As
Publication number | Publication date |
---|---|
JPS586232B2 (en) | 1983-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS55101080A (en) | Timer time display unit | |
JPS5528644A (en) | Memory unit | |
JPS5447445A (en) | Memory unit | |
JPS5447444A (en) | Memory unit | |
JPS5613573A (en) | Memory control system | |
JPS5715286A (en) | Memory device | |
JPS55163697A (en) | Memory device | |
JPS5587356A (en) | Memory circuit device | |
JPS5467337A (en) | Video memory unit | |
JPS5381018A (en) | Memory control system on disply unit | |
JPS5567865A (en) | Electronic desk computer | |
JPS5631140A (en) | Information processor | |
JPS5687147A (en) | Data recorder | |
JPS57195374A (en) | Sequential access storage device | |
JPS5533282A (en) | Buffer control system | |
JPS5715297A (en) | Memory element | |
JPS57199055A (en) | Information processing device | |
JPS6423488A (en) | Memory | |
JPS5564690A (en) | Error detection and correction system of semiconductor memory device | |
JPS5385125A (en) | Refresh memory read/write control system in display unit | |
JPS5444445A (en) | Memory control unit | |
ES450624A1 (en) | System for editing characters | |
JPS5614358A (en) | Operation log storing system | |
JPS6459692A (en) | Dram control device with page mode function | |
JPS5469919A (en) | Display unit |