JPS5447445A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5447445A
JPS5447445A JP11272377A JP11272377A JPS5447445A JP S5447445 A JPS5447445 A JP S5447445A JP 11272377 A JP11272377 A JP 11272377A JP 11272377 A JP11272377 A JP 11272377A JP S5447445 A JPS5447445 A JP S5447445A
Authority
JP
Japan
Prior art keywords
bank
signal
address
indication
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11272377A
Other languages
Japanese (ja)
Other versions
JPS586232B2 (en
Inventor
Masahiko Kida
Osamu Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52112723A priority Critical patent/JPS586232B2/en
Publication of JPS5447445A publication Critical patent/JPS5447445A/en
Publication of JPS586232B2 publication Critical patent/JPS586232B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To secure a constant access to the memory with no consciousness of the refresh cycle, by dividing the memory into two banks which memorize the same contents and refreshing one bank while the other bank is being read out. CONSTITUTION:The memory is divided into bank 5 and bank 6 which memorize the same contents. When reading is indicated, control circuit 1 selects access address signal 16 to address switch 3 and gives indication 13 to supply the signal to bank 5. At the same time, refresh RF address signal 15 is selected to address switch 4, and indication 12 is given to supply the signal to bank 6, and RF indication signal 9 is turned on to start the RF action of bank 6. Then output switch 7 receives indication 14 to select the output data, and the reading data is delivered to output data bus 18. When writing, the contents of input data bus 17 are written into the same address of the both banks via writing signal 11. (In this cycle, the RF is inhibited for both banks.)
JP52112723A 1977-09-21 1977-09-21 memory device Expired JPS586232B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52112723A JPS586232B2 (en) 1977-09-21 1977-09-21 memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52112723A JPS586232B2 (en) 1977-09-21 1977-09-21 memory device

Publications (2)

Publication Number Publication Date
JPS5447445A true JPS5447445A (en) 1979-04-14
JPS586232B2 JPS586232B2 (en) 1983-02-03

Family

ID=14593909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52112723A Expired JPS586232B2 (en) 1977-09-21 1977-09-21 memory device

Country Status (1)

Country Link
JP (1) JPS586232B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004507856A (en) * 2000-08-17 2004-03-11 マイクロン・テクノロジー・インコーポレーテッド Method and system for hiding refresh of dynamic random access memory
KR100429872B1 (en) * 2001-06-27 2004-05-04 삼성전자주식회사 Memory system for promoting efficiency of use of semiconductor memory and refresh method of the semiconductor memory
JP2012512496A (en) * 2009-05-25 2012-05-31 ソンゼ イ， Apparatus and method for implementing SRAM output characteristics in DRAM

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004507856A (en) * 2000-08-17 2004-03-11 マイクロン・テクノロジー・インコーポレーテッド Method and system for hiding refresh of dynamic random access memory
KR100429872B1 (en) * 2001-06-27 2004-05-04 삼성전자주식회사 Memory system for promoting efficiency of use of semiconductor memory and refresh method of the semiconductor memory
JP2012512496A (en) * 2009-05-25 2012-05-31 ソンゼ イ， Apparatus and method for implementing SRAM output characteristics in DRAM

Also Published As

Publication number Publication date
JPS586232B2 (en) 1983-02-03

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