JPS63282865A - Input/output circuit - Google Patents

Abstract

PURPOSE:To release a bus from a locked state and to inform the abnormality of an I/O part by outputting a false ready signal and interrupting a processor when a ready signal generating part in the I/O part is not functioned. CONSTITUTION:Since a ready signal 205 is not sent when the ready signal generating part for returning an answer to a processor 1 is not functioned, a select signal 201 and an I/O reading signal 203 are still outputted. Since a signal is inputted from a NAND gate 5 to a NAND gate 6, a clock from a clock generating circuit 3 is impressed to a clock input terminal of a timer circuit 4 through the NAND gate 6. At the time of counting up the clocks more than a regulated value, the timer circuit 4 outputs a false ready signal 206. The signal 206 is returned to the processor 1 through a NAND gate 6.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to input/output circuits.

(Conventional technology) First, a conventional input/output circuit will be explained with reference to the drawings.

The third factor is a diagram showing an example of a conventional input/output circuit, and FIG. 4 is a factor showing its operating waveform.

When the processor l writes data to the input/output unit 2, the processor l sends a select signal 401. Data signal 402 and 1/(J write signal 40411r are output.

The input/output section 2 receives a select signal 401, a data signal 402,
Based on the I10 write signal 404, a ready signal 405 is sent to the processor l at a timing when all data can be stored.
The processor l determines that writing of data to the input/output section 2 is complete based on the ready signal 405, and sends the select signal 401. data signal 402, and 1/
(Stop sending the J write signal 404.

A case in which the processor 1 reads data from the input/output unit 2 will be described with reference to the arrow. Processor 1 outputs all select signals 4011 and 110 read signals 4.3.

Input/output section 2 receives select signal 401 and input/Q +)
- After receiving the code signal 403, after a while (Ilo
It outputs a data signal 402 (which varies depending on the access time of the processor I), and at the same time returns a ready signal 405 to the processor l, meaning that the data is valid.

When the processor 1 receives the ready signal 4[)5, it reads the data and simultaneously stops sending out the select signal 401 and the I10 read signal 4(13).

In conventional input/output circuits, in order to accommodate input/output sections of varying speeds, the input/output section returns a ready signal in response to access by the processor, causing the processor to execute the entire next cycle.

(Problems to be Solved by the Invention) In the conventional input/output circuit, when the ready signal generating section that returns a response to the processor stops functioning, the ready signal is not sent f'L, so the processor does not send the select signal, There was a drawback that the bus would be locked if the data signal and I10 access signal (read or write) were all output.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and to provide an input/output circuit that does not lock the bus even if the ready generation section of the input/output section stops functioning.

(Means for Solving the Problems) In order to achieve the above-mentioned objective t-, the input/output circuit according to the present invention includes a processor that reads and writes instructions and data, and a processor that stores written data of the processor and receives data from the processor. an input/output unit that returns a ready signal when reading and writing are completed according to instructions; a clock generation circuit; It includes a gate circuit that passes the clock output from the generation circuit, and a timer circuit that counts the clock from the gate circuit and outputs a full pseudo ready signal when the clock exceeds a certain value, and the input/output section detects an abnormality. If a ready signal is not returned, a pseudo ready signal is sent back.

(Actual flow side) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a diagram showing an entire embodiment of an input/output circuit according to the present invention, and FIG. 2 is a diagram showing its operating waveforms.

When writing data to the input/output unit 2, the processor 1 outputs all of the select signal 2011, data signal 202, and write signal 2il4.

The input/output section 2 has a select signal 2()1 and a data signal 202.
and l/(J A ready signal 205 is returned to the processor l at a timing when data can be stored based on the write signal 204.

Based on the ready signal 205, the processor l determines that writing of data to the input/output unit 2 is completed, and the select signal 201, the data signal 202, and the I1010 write signal 0.
Stop sending out 4.

Next, when the processor 1 reads data from the input/output section 2, the select signal 201. and 110 read signal 203
Output.

The input/output section 2 receives a select signal 201. and l/Q read signal 203t - When received, after a while (Ilo
It outputs a data signal 202 (which varies depending on the access time of the data), and at the same time returns a ready signal 205 to the processor l indicating that the data is valid.

When processor l receives the ready signal 205, it inserts the data and at the same time stops sending out the select signal 201 and I10 read signal 203.

Next, if the ready signal generation unit that returns a response to processor l stops functioning, the ready signal 205 is not sent out, so the select signal 201 and read signal 203 remain applied. However, since the signal is input from the Nandt gate 5 to the Rinand gate 6, the clock from the clock generation circuit 3 passes through the Nantt gate 6 and is applied to the clock input terminal of the timer circuit 4.

The timer circuit 4 outputs a pseudo-ready signal 206 when the clock count exceeds a specified value.

Since the pseudo ready signal is returned to the processor l through the Nant gate 206t, even if the ready signal 205 is not generated, this cycle can be completely completed and the bus can be completely released.

At the same time, the pseudo-ready signal is input to the interrupt terminal of processor 1, and the I10 abnormality is notified.

(Effects of the Invention) As explained above, the present invention is configured so that when the ready generation section of the input/output section stops functioning, the entire pseudo ready signal is output and an interrupt is applied to the processor.
This has the effect that the bus is released from the locked state, an abnormality in the human output unit is notified, and abnormality processing can be executed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an input/output circuit according to the present invention, FIG. 2 is a diagram showing operating waveforms of the invention, FIG. 3 is a block diagram showing an example of a conventional input/output circuit, and FIG. 4 FIG. 2 is a diagram showing operating waveforms of a conventional method. 1... Processor 2... Input/output section (Ilo) 3... Clock generation circuit 4... Timer circuit

Claims (1)

[Claims] A processor that reads and writes instructions and data; an input/output unit that stores data written by the processor, reads it according to instructions from the processor, and returns a ready signal when writing is completed; and a clock generation circuit. , when either a read or a write signal is output from the processor, a gate circuit passes the clock output from the clock generation circuit, and a clock from the gate circuit is counted, and if the clock exceeds a certain value. and a timer circuit that outputs a pseudo ready signal when the input/output section is abnormal and the ready signal is not returned, the input/output circuit is configured to return the pseudo ready signal.