JPS57728A - Monitoring device - Google Patents

Monitoring device

Info

Publication number
JPS57728A
JPS57728A JP7394880A JP7394880A JPS57728A JP S57728 A JPS57728 A JP S57728A JP 7394880 A JP7394880 A JP 7394880A JP 7394880 A JP7394880 A JP 7394880A JP S57728 A JPS57728 A JP S57728A
Authority
JP
Japan
Prior art keywords
signal
bus
counter
input
output equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7394880A
Other languages
Japanese (ja)
Other versions
JPS6037936B2 (en
Inventor
Yoshimi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55073948A priority Critical patent/JPS6037936B2/en
Publication of JPS57728A publication Critical patent/JPS57728A/en
Publication of JPS6037936B2 publication Critical patent/JPS6037936B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the functions of the whole system from stopping owing to a partial fault, by generating a pseudo response signal from a monitoing device when there is no response signal arriving from an input and output equipment even a prescribed time later, and then by displaying the address of the input and output equipment.
CONSTITUTION: When a read request signal RREQ or write request signal WREQ sent from a microprocessor via a bus 1a to an input and output equipment is received by a monitoring device 1, a counter 6 starts counting and when a response signal RESP from the input and output equipment is received, the counter 6 is reset. If the signal RESP is not received even a prescribed time after the signal RREQ or WREQ is outputted, the counter 6 outputs a pseudo signal RESP to the bus 1a. Consequently, a processor releases a stand-by state to advance steps, and the counter 6 opens a gate 2 with a gate signal 4b to lead the bus of the bus 1a to a storage circuit 3, thereby displying its contents on a display circuit 4 with a control signal 4a.
COPYRIGHT: (C)1982,JPO&Japio
JP55073948A 1980-05-30 1980-05-30 monitoring device Expired JPS6037936B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55073948A JPS6037936B2 (en) 1980-05-30 1980-05-30 monitoring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55073948A JPS6037936B2 (en) 1980-05-30 1980-05-30 monitoring device

Publications (2)

Publication Number Publication Date
JPS57728A true JPS57728A (en) 1982-01-05
JPS6037936B2 JPS6037936B2 (en) 1985-08-29

Family

ID=13532816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55073948A Expired JPS6037936B2 (en) 1980-05-30 1980-05-30 monitoring device

Country Status (1)

Country Link
JP (1) JPS6037936B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63282865A (en) * 1987-05-15 1988-11-18 Nec Corp Input/output circuit
JPS6468858A (en) * 1987-09-09 1989-03-14 Nec Corp Microprocessor peripheral circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63282865A (en) * 1987-05-15 1988-11-18 Nec Corp Input/output circuit
JPS6468858A (en) * 1987-09-09 1989-03-14 Nec Corp Microprocessor peripheral circuit

Also Published As

Publication number Publication date
JPS6037936B2 (en) 1985-08-29

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