JPS5660962A - Display method for normal operation of central processing unit - Google Patents

Display method for normal operation of central processing unit

Info

Publication number
JPS5660962A
JPS5660962A JP13638779A JP13638779A JPS5660962A JP S5660962 A JPS5660962 A JP S5660962A JP 13638779 A JP13638779 A JP 13638779A JP 13638779 A JP13638779 A JP 13638779A JP S5660962 A JPS5660962 A JP S5660962A
Authority
JP
Japan
Prior art keywords
cpu4
normal operation
timer
signal
analyzer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13638779A
Other languages
Japanese (ja)
Inventor
Ryohei Yabe
Hiroshi Hashimoto
Kiwao Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13638779A priority Critical patent/JPS5660962A/en
Publication of JPS5660962A publication Critical patent/JPS5660962A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to display only the normal operation that CPU executes a program normally, by displaying only the operation state by using the respose signal of CPU to external signals arriving at constant intervals.
CONSTITUTION: In the constitution of analyzer 1, timer 2, memory 3, and CPU4, CPU4 controls analyzer 1 by the program stored in memory 3 to perform data processing. In this case, timer 2 is generally equipped to the processing system and timer 2 sends an interruption signal to CPU4 at constant intervals. After outputting a reset signal for this interruption signal to timer 2, CPU4 controls analyzer 1 according to the program. Since this interruption reset signal is not outputted unless CPU4 is in normal operation, using this signal provides the desired normal operation display.
COPYRIGHT: (C)1981,JPO&Japio
JP13638779A 1979-10-24 1979-10-24 Display method for normal operation of central processing unit Pending JPS5660962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13638779A JPS5660962A (en) 1979-10-24 1979-10-24 Display method for normal operation of central processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13638779A JPS5660962A (en) 1979-10-24 1979-10-24 Display method for normal operation of central processing unit

Publications (1)

Publication Number Publication Date
JPS5660962A true JPS5660962A (en) 1981-05-26

Family

ID=15173957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13638779A Pending JPS5660962A (en) 1979-10-24 1979-10-24 Display method for normal operation of central processing unit

Country Status (1)

Country Link
JP (1) JPS5660962A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59214953A (en) * 1983-05-20 1984-12-04 Olympus Optical Co Ltd Device for preventing microprocessor from malfunction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59214953A (en) * 1983-05-20 1984-12-04 Olympus Optical Co Ltd Device for preventing microprocessor from malfunction
JPH0440014B2 (en) * 1983-05-20 1992-07-01 Olympus Optical Co

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