JPS5687145A - Monitor system for microcomputer - Google Patents

Monitor system for microcomputer

Info

Publication number
JPS5687145A
JPS5687145A JP16517579A JP16517579A JPS5687145A JP S5687145 A JPS5687145 A JP S5687145A JP 16517579 A JP16517579 A JP 16517579A JP 16517579 A JP16517579 A JP 16517579A JP S5687145 A JPS5687145 A JP S5687145A
Authority
JP
Japan
Prior art keywords
signal
program
content
fed
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16517579A
Other languages
Japanese (ja)
Inventor
Tsuguyoshi Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16517579A priority Critical patent/JPS5687145A/en
Publication of JPS5687145A publication Critical patent/JPS5687145A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To monitor the operation scarcely discontinuing the execution of program, by performing the detection of a break pint in hardware mode, and displaying the content of the program status of a CPU and the content of a register at the break point.
CONSTITUTION: The mode set circuit 3 sets the break point, enters the execution program and the address comparator 7 compares the program address signal (a) with the preset break point address signal (b), and the coincidence signal (f) is fed to the AND circuit 11. The logic with the status stroke signal (e) is taken at the circuit 11, the AND signal (g) is set to RSFF12, and the interruption signal (n) is fed to CPU1. Further, the content of program status and the register are shunted to the external memory, the interruption erasing signal (p) is output to the output port 13, the reset signal (q) is fed to FF12 from the port 13, the interruption signal (n) is erased, the content is displayed and the operation is controlled that the program execution is immediately restored.
COPYRIGHT: (C)1981,JPO&Japio
JP16517579A 1979-12-18 1979-12-18 Monitor system for microcomputer Pending JPS5687145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16517579A JPS5687145A (en) 1979-12-18 1979-12-18 Monitor system for microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16517579A JPS5687145A (en) 1979-12-18 1979-12-18 Monitor system for microcomputer

Publications (1)

Publication Number Publication Date
JPS5687145A true JPS5687145A (en) 1981-07-15

Family

ID=15807270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16517579A Pending JPS5687145A (en) 1979-12-18 1979-12-18 Monitor system for microcomputer

Country Status (1)

Country Link
JP (1) JPS5687145A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPS626341A (en) * 1985-07-02 1987-01-13 Nec Corp Information processor
JPS644844A (en) * 1987-06-29 1989-01-10 Hitachi Electronics Debugging device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPS626341A (en) * 1985-07-02 1987-01-13 Nec Corp Information processor
JPS644844A (en) * 1987-06-29 1989-01-10 Hitachi Electronics Debugging device

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