JPS644844A - Debugging device - Google Patents

Debugging device

Info

Publication number
JPS644844A
JPS644844A JP62159625A JP15962587A JPS644844A JP S644844 A JPS644844 A JP S644844A JP 62159625 A JP62159625 A JP 62159625A JP 15962587 A JP15962587 A JP 15962587A JP S644844 A JPS644844 A JP S644844A
Authority
JP
Japan
Prior art keywords
memory
fifo
ram
program
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62159625A
Other languages
Japanese (ja)
Inventor
Hiromi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP62159625A priority Critical patent/JPS644844A/en
Publication of JPS644844A publication Critical patent/JPS644844A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To facilitate debugging to a program of various devices loaded with a microprocessor, by indicating clearly in a real time a state of a data access to a specific address, and also, storing a display data and confirming repeatedly its data with respect to an abnormal phenomenon of non-appearance. CONSTITUTION:The titled device is provided with a microcomputer 1 for executing a control of a memory mode operation as a real time function (j) and a memory function, an FIFO memory 12 for mentioning the contents of a memory 9, and a ROM 16 in which a control program of a memory mode operation is stored. Also, this device is provided with a CPU RAM 15 for holding temporarily an external address signal at the time of a memory mode, an FIFO RAM 14 for holding temporarily the contents of the FIFO memory 12, an FIFO, an FIFO RAM, a RAM controller 17 for applying a control signal to a buffer circuit 5, and an I/O controller 13 for applying a control signal to the RAM controller 17. In such a way, an abnormal phenomenon can be confirmed repeatedly, and an error on a program is detected in its early stage.
JP62159625A 1987-06-29 1987-06-29 Debugging device Pending JPS644844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62159625A JPS644844A (en) 1987-06-29 1987-06-29 Debugging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62159625A JPS644844A (en) 1987-06-29 1987-06-29 Debugging device

Publications (1)

Publication Number Publication Date
JPS644844A true JPS644844A (en) 1989-01-10

Family

ID=15697809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62159625A Pending JPS644844A (en) 1987-06-29 1987-06-29 Debugging device

Country Status (1)

Country Link
JP (1) JPS644844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424836A (en) * 1990-05-18 1992-01-28 Fujitsu Ltd Microprocessor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687145A (en) * 1979-12-18 1981-07-15 Mitsubishi Electric Corp Monitor system for microcomputer
JPS58213353A (en) * 1982-06-04 1983-12-12 Fuji Xerox Co Ltd Forced loop circuit
JPS62127949A (en) * 1985-11-29 1987-06-10 Fujitsu Ltd Debug system for digital signal processing processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687145A (en) * 1979-12-18 1981-07-15 Mitsubishi Electric Corp Monitor system for microcomputer
JPS58213353A (en) * 1982-06-04 1983-12-12 Fuji Xerox Co Ltd Forced loop circuit
JPS62127949A (en) * 1985-11-29 1987-06-10 Fujitsu Ltd Debug system for digital signal processing processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424836A (en) * 1990-05-18 1992-01-28 Fujitsu Ltd Microprocessor

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