JPS62127949A - Debug system for digital signal processing processor - Google Patents

Abstract

PURPOSE:To debug a program in real time by acquiring an internal signal processing data of a digital signal processing means and extracting it externally when execution procedure information of a digital signal processing program and given acquisition instruction information have a prescribed relation. CONSTITUTION:Information 123 representing the execution order of a program 111 is compared with acquisition instruction information 119, and when they are in a prescribed relation, an acquisition acting signal 125 is fed to an acquisition means 129. The acquisition means 129, in receiving the acquisition acting signal 125, extracts a digital signal processing data 115 externally. The execution digital signal processing data 115 in the program execution order represented by the acquisition instruction information 119 is extracted externally. Thus, the data is extracted in real time without giving any effect onto the signal processing and the program is debugged in real time by using the extracted data.

Description

[Detailed Description of the Invention] [Summary] A debugging method for a digital signal processing processor, in which if execution order information of a digital signal processing program and given capture command information are in a predetermined relationship, the digital signal processing means debugs the digital signal processing means. By configuring the system to capture internal signal processing data and retrieve it externally, the program can be debugged in real time by outputting the processed data externally in real time without affecting the operation of digital signal processing. I did it like that.

[Industrial use of bones! ]

The present invention relates to a debugging method for a digital signal processor.

For example, a speech recognition device is equipped with a one-chip LSI for a digital signal processing processor (DSP), and the program for processing the speech signal inside the device is stored in a ROM.
is stored in. Digital signal processing is performed in accordance with the execution of this program. By the way, it is necessary to check (debug) whether the program to be stored in the ROM is installed as desired and operates as specified.

[Conventional technology]

Program debugging methods that have conventionally been adopted to meet such demands have been exclusively static. In other words, by tracing the DSPLS I program step by step, the contents of the program execution at that time are examined in an orderly manner, and steps in which the predetermined contents do not occur are searched for. This made program debugging possible.

[Problem that the invention seeks to solve]

However, such conventional methods involve static debugging and are effective for processors that do not involve real-time processing; It was not suitable for DSP. There was a desire to be able to debug programs while performing real-time processing on actual voice input.

In order to satisfy such a request, it is necessary to perform real-time processing and extract the processed data during that process, and when extracting it, it is necessary to make sure that there is no influence on the real-time processing in the DSP. must not be given.

The present invention was created in view of these points, and an object of the present invention is to provide a debugging method for a digital signal processor that extracts processed data in real-time processing and debugs a program.

[Means for solving problems]

FIG. 1 is a principle block diagram of a debugging method for a digital signal processor according to the present invention.

In the figure, a storage means 113 stores a program 111 for performing digital signal processing.

The signal processing means 117 performs digital signal processing by executing the program 111, and internally generates digital signal processing data 115 based on the execution result.

Command means 121 provides capture command information 119.

The capture energizing means 127 receives the execution order information 123 of the program 111 and the capture command information 119, and generates a capture energizing signal 125 when both pieces of information have a predetermined relationship.

The capture means 129 captures the digital signal processing data 115 in response to the capture activation signal 125 and takes it out of the signal processing means 117 .

Therefore, as a whole, the digital signal processing data 1 is processed in the program execution order corresponding to the capture command information 119.
15 is taken out to the outside.

[Effect]

The information 123 representing the execution order of the program 111 is
It is compared with the capture command information 119, and if a predetermined relationship is established, a capture activation signal 125 is supplied to the capture means 129.

The capture means 129 takes out the digital signal processing data 115 to the outside when the capture activation signal 125 is supplied.

Executed digital signal processing data 115 in the program execution order represented by captured instruction information 119 is retrieved to the outside.

In the present invention, the order in which the program is executed in real time is commanded and the processing data in that order is retrieved, so that there is no influence on the signal processing operation in real time. This makes it possible to retrieve data without any problems, and the program can be debugged in real time using the retrieved data.

〔Example〕

FIG. 2 shows an embodiment of the present invention. Here, DSP21
0 is a ROM 211 in which a program to be currently targeted by the Deva Knob is stored, a program counter (PC) 215 that outputs an address signal 213 for sequentially reading out the program according to the address, and a program counter (PC) 215 that outputs an address signal 213 for sequentially reading out the program according to the address. Two instruction registers (IRE) 217 that store instructions to be executed.
In addition to (IR2) 219, Lusokua to Sodo decoder (
LAD DEC) 221 is included.

Furthermore, the system clock signal 225 that regulates the overall operation of this DSP 210 is connected to two AND gates 227 and 2.
29, and each of these AND gates 227 and 229 receives an IR1 enable signal 231.
An IR2 enable signal 233 is supplied to each.

The output signals 235 and 237 of both AND gates 227 and 229 are sent to the corresponding instruction register 21.
7,219.

Furthermore, the DSP 210 has an internal data bus 241 on which data etc. are loaded, and two registers 243 and 245 that take in the data in the bus 241. Arithmetic and logical operation Uniso I-(ALU) that performs operations
247, register 249 to which the calculation result is given, hash 2
R to which data is written and read from and to 41
It is equipped with AM251 etc.

Externally to the DSP 210 formed in this way, the address signal 2 from the program counter 215 is
Two registers 261 and 263 are supplied with register enable signals 231 and 233, and two gates 265 and 267 are supplied with register enable signals 231 and 233.

The respective output signals of these gates 265 and 267 are applied to both registers 261 and 263, respectively.

Further, a register 273 to which the program address information signal 271 to be searched (captured) is supplied, and a comparator 279 to which the register output signal 275 and the output signal 277 of the previous register 263 are supplied are added. 279 comparison output signal 281 is DS
The signal is applied to the decoder 221 of P210.

Furthermore, an external RAM 295 is connected to the internal data bus 241 in the DSPIIO via gates 291A and 291B, and storage means for taking in data on the bus 241 is also connected.

FIGS. 3A to 3G are timing diagrams illustrating the operation of the embodiment of the present invention.

By the way, in normal audio band signal processing, processing is often performed in the order according to the signal flow, as generally represented by a signal flow graph. In that case, the program flow and signal flow match.

Now, FIG. 4 shows ADPCM as an example of signal flow. When debugging a program with such a signal flow, by monitoring the signals at points a, b, c, and d in the figure, it becomes possible to debug the program in a correlated manner. To do this, the address of the instruction being executed by the DSP 210 is externally compared with the address at the time when the signal (data) at point a is output to the internal data bus 241, for example, and when they match, the DSP 210
All you have to do is send a capture signal to

The operation of the embodiment of the present invention will be explained based on the above premise.

In FIG. 2, an address signal 213 is generated from a program counter 215 (see FIG. 3(A)). Here, the "n" command is the signal (data) at point 0 in Figure 3.
Assume that this is an instruction to store in memory (RAM).

Therefore, when the address of such "n" instruction is supplied from the program counter 215 to the ROM 211,
The instruction is output from the ROM 211 to the first instruction register 217.

Now, both instruction register enable signal 2
Assuming that both registers 217 and 313 are maintained at a "high" logic level, instructions from ROM 211 are sequentially stored in both registers 217 and 219 in response to system clock signal 225.
The signal is supplied to the DEC 221. In this case, the transition states of instructions in both instruction registers 217 and 219 are shown in FIGS. 3(B) and 3(C).
)become that way.

In addition, both instruction register enable signals 2
31 and 233 are also supplied to both gates 265 and 267, so address information representing program execution instructions is sequentially stored in both registers 261 and 263. Therefore, the instruction address represented by the output signal 277 of the register 263 is
19 to the decoder 221 in terms of time.

If the address of the instruction "n" is previously stored in the register 273 as a program address information signal 271 for capture, an output signal 275 for data capture representing information corresponding to the address is constantly generated.

Therefore, in comparator 279, signal 275 and signal 2
77, that is, when both address information match, a comparison output signal 281 for capture activation which becomes a "high" logic level is generated (see FIG. 3(D)). In response to this signal 281, the decoder 221 outputs a debug data enable signal and a depack data write signal to the outside of the DSP 210, as shown in FIGS. 3(E) and 3(F). At the same time, the internal data bus control signal 297
Output to 1A. Thereby, internal data bus 24
The internal signal processing digital data currently stored in DSP 210 is captured, output to the outside of the DSP 210, and stored in a capturing storage means (not shown). Therefore, the signal processor digital data resulting from the instruction execution at the 0 point shown in FIG. 4 is output from the DSP 210 to the outside (see FIG. 3 (G)).

In this way, it is possible to debug a program being executed on the DSP in real time by outputting internal data from the execution of an instruction at a certain predetermined search address to the outside and examining the output data.

In the above embodiment, a DSP was taken as an example, but the present invention can be implemented in other processors in a system environment that requires real-time debugging as described above.

〔Effect of the invention〕

As detailed above, according to the present invention, processing digital data at a certain address is sent to the DSP in real time.
The data can be taken out without affecting the processing operation of the program, and in particular, it becomes possible to debug the program, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a debugging method for a digital signal processor according to the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the present invention, and FIG.
Figures (A) to (G) are timing diagrams for explaining the operation of the embodiment of the present invention, and Figure 4 is an explanatory diagram showing an example of an ADPCM signal flow graph. In FIG. 1, 111 is a program, 113 is a storage means, 115 is digital signal processing data, 117 is a signal processing means, 119 is capture command information, 121 is a command means, 123 is execution order information, and 125 is a capture activation signal. , 127 is a trapping/energizing means, and 129 is a trapping means. In FIG. 2, 210 is a digital signal processor (DSP), 211
is ROM. 213 is an address signal, 221 is a look ahead decoder (LAD DBC)
, 251 is a RAM, 273 is a register, 279 is a comparator, 281 is a comparison output signal, 291A and B are gates, 295 is an external RAM, and 297 is an internal data bus control signal. \ku= Figure 1

Claims (1)

[Claims] Program (111) for performing digital signal processing
a signal processing means (117) that performs digital signal processing by executing the program and internally generates digital signal processing data (115) as the execution result; and capture command information. (119); receiving the program execution order information (123) and the capture command information, and generating a capture activation signal (125) when both pieces of information have a predetermined relationship; Capturing and biasing means (127)
and a capturing means (129) for capturing the digital signal processing data and taking it out of the signal processing means in response to the capturing energizing signal, and capturing the digital signal processing data in real time using the digital signal processing data. A debugging method for a digital signal processing processor, characterized in that it is configured to perform debugging.