JP2000089977A - Debugging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make debugging operation efficient by receiving the start address of a function to be debugged and the program counter value of a target processor which executes a target program, compairing them with each other and outputting a matching result when they are matched with each other. SOLUTION: The start address of the function to be debugged is set and registered in an address comparing circuit 2 and at the same time, error condition of the function are set and registered in a function error condition comparing circuit 5. In this state, an MCU 1 executes the target program including the function to be debugged. The target program is executed, and the program counter value is compared with the start address of the function. When they match each other, a return address acquiring circuit 3 acquires a return address according to specific register rewrite information or register rewrite information of the MCU 1, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging system for debugging a function set as a specific processing unit at the time of developing and designing a program in a high-level language.

[0002]

2. Description of the Related Art Conventionally, as a procedure for developing and designing a program in a high-level language, for example, a specific processing unit that can be arbitrarily set by a development designer in accordance with the contents of the program, for example, before starting a predetermined process, A method of defining a process for securing a memory area necessary for the process and a process such as a spreadsheet as a function and constructing a program has been adopted. In a conventional debugging system for debugging a program developed and designed by such a method, the concept of a function unit is not defined when recognizing a target program. That is, the conventional debugging system cannot recognize each specific process defined as a function as a function unit. In such a debugging system, when debugging a function that constitutes a program, the function executes the function to be debugged by executing the entire program included as a subroutine, for example, and the function obtained after the execution of the function is completed The debugger has to manually stop the program at an appropriate position and check whether the return value of the program is normal or not while paying attention to the structure of the compiler. Also, when checking with the trace data collected during the execution of the function, obtain all execution results, pick up the trace data at the time of error occurrence from among them, and perform the above check manually by the debug worker. I was going.

[0003]

As described above,
In a conventional bag system, since there is no concept of a function unit, debugging of a function included in a target program to be debugged often depends on the manual work of a debugger, and the debugging work takes time and effort. , Resulting in inefficiency.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a debugging system which facilitates debugging of a function and improves the efficiency of debugging work. .

[0005]

In order to achieve the above object, the invention according to claim 1 includes a function set as a specific processing unit at the time of program development design, and debugging of the function is performed in function units. The target processor that executes the target program to be executed and the start address of the function to be debugged and the program counter value of the target processor are compared, and the two are compared. When they match, a match result is output, and the match is output. A first comparison circuit instructing collection of trace data in accordance with the instruction, and receiving a match result output from the first comparison circuit, based on predetermined register rewrite information, an address bus value, and a data bus value of the target processor. To obtain the return address that is the return address after the execution of the function to be debugged Receiving the return address obtained by the return address obtaining circuit and the program counter value of the target processor, comparing the two, outputting a match result when the two match, and stopping the trace data collection. In response to the instructed second comparison circuit and the matching result output from the second comparison circuit, an error of the debug target function whose execution has been completed is determined based on a previously input error condition, and an error occurs. And an error discriminating circuit for instructing the storage of the trace data in the case where the error has occurred.

According to a second aspect of the present invention, there is provided a target processor for executing a target program which includes a function set as a specific processing unit at the time of program development and design, and the debug operation of the function is performed in function units. A first comparison circuit that receives a start address of a function and a program counter value of a target processor, compares the two, and outputs a match result when they match, and receives a match result output from the first comparison circuit. hand,
Predetermined register rewrite information of the target processor,
A return address acquisition circuit for acquiring a return address which is a return address after execution of the function to be debugged based on the address bus value and the data bus value; a return address acquired by the return address acquisition circuit; The second comparison circuit receives the counter value, compares the two, and outputs a match result when the two match, and receives a match result output from the second comparison circuit, and based on the error condition input in advance. An error determining circuit that determines an error of the debug target function whose execution has been completed and stops the execution of the program of the target processor according to a previously input instruction when an error occurs.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a debugging system according to an embodiment of the present invention.

In FIG. 1, a debug system includes a function set as a specific processing unit at the time of program development design, and this function is an MCU 1 serving as a target processor for executing a target program to be debugged in function units; Upon receiving the start address (B) of the function and the program counter (PC) value (C) of the MCU1, the two are compared, and when they match, a pulse signal of the matching result is output when they match, and An address comparing circuit 2 for instructing collection when collecting trace data according to a previously input instruction;
Upon receiving the match result output from the address comparison circuit 2,
Referring to the register rewrite information output from the MCU 1 as the predetermined register value (F) and the address bus value (D) and the data bus value (E) output from the MUC 1, for example, execution of a subroutine function Return address acquisition circuit 3 that acquires a return address (J) that is a return address to the main routine when the process is completed, and receives the return address acquired by the return address acquisition circuit 3 and the program counter value of the MCU 1 and compares them. And a return address comparison circuit 4 for outputting a pulse signal of the coincidence result when the two coincide with each other as the comparison result (H), and instructing to stop the collection of the trace data when the trace data is being collected; In response to the matching result output from the address comparing circuit 4, M
A register value (F) serving as register rewrite information of a predetermined register given from CU1, or this value and MUC1
By comparing the return value after completion of the function, which is obtained by referring to the address bus value and the data bus value, with the function error condition (A) input in advance, the error of the debug target function whose execution has been completed is determined. , Comparison result (I)
And a function error condition comparison circuit 5 for instructing storage / discarding of trace data or a break in program execution according to the presence or absence of an error.

In such a configuration, before debugging, first, as shown in FIG. 2, for example, a function list described in the debug information is displayed on a screen by a debugger, and the debugger attempts to debug. Error conditions for each function, whether or not to acquire trace data,
Enter whether there is a break. In FIG. 2, with respect to the functions of subroutines sub1, sub2, and sub3 displayed on the screen by the debugger, for example, the function sub1 acquires trace data, and sets a return value (sub1) <0 as an error condition, An input is set so that a break is not performed when an error occurs. In the function sub2, no trace data is acquired. As an error condition, a return value (sub2) = NULL is set. And the global variable (g
Int) <0, and an input is set so that a break is not performed when an error occurs.

The operation of the debug system by the debugger and the simulator when the acquisition of the trace data is set after the input setting is completed will be described with reference to an output signal timing chart shown in FIG.

First, the start (head) address of the function to be debugged is set and registered in the address comparison circuit 2, and at the same time, the error condition of the function is set and registered in the function error condition comparison circuit 5. In such a state, the target program including the function to be debugged is executed by the MCU 1, the execution of the target program proceeds, and the program counter value is compared with the start address of the function set and registered in the address comparison circuit 2. If they match,
Predetermined register rewrite information of MCU1, or MCU1
The return address is obtained by the return address obtaining circuit 3 based on the register rewriting information, the address bus value and the data bus value. At the same time, the start of the trace data collection is given as a pulse signal as shown in FIG. 3 to a trace circuit (not shown) and instructed.

Here, the method of obtaining the return address is as follows.
It depends on the MCU 1 that is the target processor. In a processor employing the link register method, a return address is set in a specific register, and the return address is specified from the rewrite information of the register. On the other hand, in a processor adopting the stack method, the return address is set in the stack memory. Therefore, the return address is specified from the immediately preceding stack memory rewrite information and the address bus value and data bus value of the MCU 1.

Next, the obtained return address is input to the return address comparison circuit 4, and the return address and the program counter value are compared by the return address comparison circuit 4, and the execution of the function to be debugged is completed. When they match, the stop of the collection of the trace data is given to the trace circuit as a pulse signal as shown in FIG. At the same time, as described above, the error condition set and registered in the function error condition comparison circuit 5 is determined, and when an error occurs, a pulse signal for storing trace data is output to the function error condition comparison circuit. 5 is output as the comparison result (I), and when the trace data is stored in the temporary holding trace buffer, the trace data stored in the temporary holding trace buffer is transferred to the common trace buffer, or Is stored in the common trace buffer from the beginning, a rewrite inhibition flag is set to prevent the stored trace data from being deleted. On the other hand, if no error has occurred, the trace data stored in the trace buffer is discarded.

As described above, by employing the above-mentioned debugging system, when the target program is executed and the function is executed, trace data of the executed function is obtained and used for the execution trace and the argument of the function. The state of registers and memory is recorded, and it is determined whether an error has occurred in the executed function.This eliminates the need for a debug worker to manually debug each function as in the past, and replaces the function with a function. Debugging can be easily performed in units, and the debugging efficiency of functions can be improved.

Next, the operation of the debug system by the debugger and the simulator when a break is set when an error occurs will be described with reference to an output signal timing chart shown in FIG.

First, the start (head) address of the function to be debugged is set and registered in the address comparison circuit 2, and at the same time, the error condition of the function is set and registered in the function error condition comparison circuit 5. In such a state, the target program including the function to be debugged is executed by the MCU 1, the execution of the target program proceeds, and the program counter value is compared with the start address of the function set and registered in the address comparison circuit 2. If they match,
The return address is obtained by the return address obtaining circuit 3 based on the register rewrite information of the MCU 1 or the register rewrite information of the MCU 1, the address bus value, and the data bus value. The method of obtaining the return address is performed in the same manner as described above.

Next, the obtained return address is input to the return address comparison circuit 4, and the return address is compared with the program counter value by the return address comparison circuit 4, and the execution of the function to be debugged is completed. Are matched, the error condition set and registered in the function error condition comparison circuit 5 is determined. If an error occurs, a break signal is output to the function error condition comparison circuit 5.
Is output to the MCU 1 as the comparison result (I), whereby the instruction execution of the MCU 1 is stopped.

As described above, in the above-described embodiment, when an error occurs, the execution of the target program is stopped, so that the debug operator does not have to manually debug each function as in the prior art, and the function is replaced with the function. Debugging can be easily performed in units, and the debugging efficiency of functions can be improved.

[0020]

As described above, according to the present invention, the debugging system for debugging the functions included in the target program in units of functions is employed, so that the functions included in the target program can be easily debugged in a short time. And the efficiency of the debugging operation can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a debugging system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a screen display example of a function list described in debug information by a debugger.

FIG. 3 is a diagram showing a timing chart of output signals in the system shown in FIG. 1;

[Explanation of symbols]

 1 MCU 2 Address comparison circuit 3 Return address acquisition circuit 4 Return address comparison circuit 5 Function error condition comparison circuit

Claims (2)

[Claims] 1. A target processor for executing a target program which includes a function set as a specific processing unit at the time of program development design, and a debug operation of the function is performed in function units, a start address of a function to be debugged, A first comparison circuit that receives the program counter value of the target processor, compares the two, outputs a match result when the two match, and instructs to collect trace data according to a previously input instruction; Upon receiving the matching result output from the comparing circuit, a return address to be a return address after the execution of the function to be debugged is obtained based on predetermined register rewrite information, an address bus value, and a data bus value of the target processor. Obtained by return address acquisition circuit and return address acquisition circuit A second comparison circuit that receives the return address and the program counter value of the target processor, compares the two, outputs a match result when they match, and instructs to stop the collection of trace data; Based on the matching result output from the circuit, based on an error condition input in advance, an error of the debug target function that has been executed is determined, and if an error occurs, an error determination instructing saving of trace data is performed. A debugging system, comprising: a circuit; 2. A target processor for executing a target program including a function set as a specific processing unit at the time of program development design, and a debug operation of the function is performed on a function basis; a start address of the function to be debugged; A first comparison circuit that receives the program counter value of the target processor and compares the two, and outputs a match result when the two match; a first comparison circuit that receives the match result output from the first comparison circuit; A return address acquisition circuit that acquires a return address that is a return address after the execution of the function to be debugged based on the register rewriting information, the address bus value, and the data bus value of the debugger, and a return address acquired by the return address acquisition circuit. And target processor program counter A second comparison circuit that receives the value and compares the two, and outputs a match result when the two match, and receives a match result output from the second comparison circuit, based on an error condition input in advance. An error discriminating circuit for discriminating an error of the function to be debugged whose execution has been completed and, when an error has occurred, stopping execution of the program of the target processor in accordance with a previously input instruction. .