JP2754899B2 - Return address monitoring circuit of debug device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program error detecting means of a debugging device that executes a program and corrects a program error.

[Prior Art] FIG. 2 is a configuration diagram showing a conventional debug device, and shows a configuration example of a portion for detecting values of an address bus and a data bus in real time.

In FIG. 2, 1 is a microcomputer to be debugged, and 2 is a device (ROM, RAM, peripheral IC) responding to a read / write cycle of the microcomputer.
Etc.) 3 is a comparison data latch for latching a value of an address bus 5 and a data bus 6 to be detected specified by a user who operates the debugging device, and 4 is an address bus 5 of the value of the comparison data latch 3 and an output of the microcomputer 1. A comparator for detecting a match with the value of the data bus 6, and 7 is a control bus.

 Next, the operation will be described.

The comparator 4 compares the value of the address bus 5 output by the microcomputer 1 for accessing the device 2 with the value set in the comparison data latch 3. When comparing,
By comparing the signals of the control bus 7 output from the microcomputer 1 together, a specific access to a specific address of the microcomputer 1 can be detected. Next, using the coincidence detection signal, operations such as stop of program execution and start of real-time trace are performed.

The value of the data bus 6 when the microcomputer 1 reads / writes the device 2 is compared with the value set in the comparison data latch 3 by the comparator 4. When comparing,
By comparing the signals of the control bus 7 output from the microcomputer 1 together, it is possible to detect a specific access of the microcomputer 1 to specific data. Then
Using the coincidence detection signal, operations such as stop of program execution and start of real-time trace are performed.

By combining the above, it is possible to detect operations such as reading / writing specific data to a specific address.

[Problems to be solved by the invention]

In the conventional debug device, it was possible to detect writing of specific data to a specific address and to detect specific access to a specific address. However, it is necessary to match a return address saved at the time of a subroutine call with a return address extracted at the time of return. It was impossible to detect.

The present invention has been made in view of such a point,
An object of the present invention is to realize a debugging device capable of monitoring in real time whether a return address saved by a microcomputer at the time of a subroutine call matches a return address retrieved by the microcomputer at the time of return.

[Means for solving the problem]

In order to achieve such an object, the present invention compares a return address saved in a stack area at the time of a subroutine call of a microcomputer to be debugged with a return address written in a storage circuit at the time of a subroutine call in real time at the time of return. A comparison circuit is provided.

[Action]

In the return address monitoring circuit of the debugging device according to the present invention, the comparison between the return address saved by the microcomputer at the time of the subroutine call and the return address taken out by the microcomputer at the time of the return is based on the value of the data saved in the stack area by the subroutine call instruction. This is performed by sequentially storing the value of the address to which the value is written, and comparing the value of the data extracted by the return instruction and the value of the address from which the value is read with the stored value.

〔Example〕

FIG. 1 is a configuration diagram showing a debug device to which an embodiment of a return address monitoring circuit according to the present invention is applied. FIG. 1 shows only the part directly related to the return address coincidence detection.

In FIG. 1, 1 is a microcomputer to be debugged, 2 is a memory serving as a stack area, 4 is a comparison circuit, 5 is an address bus, 6 is a data bus, 7 is a control bus, 8 is a data bus 6, and control is An instruction decoder that monitors the bus 7 and detects a subroutine call instruction and a return instruction, 9 is a storage circuit that stores data and address values saved by the subroutine call instruction, and 10 is a debug device control unit that controls the entire debug device. It is. The comparison circuit 4 compares the data fetched from the memory 2 by the return instruction and the value of the address with the corresponding value in the storage circuit 9.

Next, the operation of this embodiment will be described with reference to FIG. When executing the subroutine call instruction, the microcomputer 1 saves the return address in the memory 2. At the same time, the instruction decoder 8 detects the execution of the subroutine call instruction, and writes the return address value saved by the microcomputer 1 and the address of the memory used for saving into the storage circuit 9. The storage circuit 9 has a FILO (First In Last Out) circuit configuration in which a previously written value is read later. Reading from the storage circuit 9 is performed by executing a return instruction.

Next, when the microcomputer 1 executes the return instruction, it retrieves the return address from the memory 2.
At the same time, the instruction decoder 8 detects the execution of the return instruction,
The comparison circuit 4 compares the value of the address output by the microcomputer 1 for extracting the return address and the data output by the memory 2 with the corresponding value of the storage circuit 9. In the comparison circuit 4, when the values do not match, the debug device control unit 10 sends a mismatch detection signal a. The debug device control unit 10 performs operations such as stopping the execution of the microcomputer 1, and the debug device notifies the programmer of the mismatch of the return addresses.

In the above embodiment, only the combination of the subroutine call instruction and the return instruction is shown. In addition to the above, the combination of the software interrupt instruction and the return instruction from the interrupt, and the hardware interrupt and the interrupt due to internal / external factors are also used. May be used.

Furthermore, it goes without saying that the above three combinations may be used alone or in combination.

〔The invention's effect〕

As described above, the present invention compares the return address saved in the stack area at the time of a subroutine call with the return address written to the storage circuit at the time of the subroutine call in real time at the time of return, so that the stack pointer changes due to a program error. Thus, the abnormal operation of the microcomputer after the execution of the return instruction can be detected during the real-time operation, and there is an effect that the debugging time can be reduced by finding a program error.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a debug device to which an embodiment of a return address monitoring circuit according to the present invention is applied, and FIG. 2 is a block diagram showing a conventional debug device. 1 ... microcomputer, 2 ... memory, 4 ... comparison circuit, 5 ... address bus, 6 ... data bus, 7 ...
... Control bus, 8 ... Instruction decoder, 9 ... Storage circuit, 10
... Debug device control unit.

Claims (1)

(57) [Claims] In a debugging apparatus for executing a program and correcting an error in the program, a return address saved in a stack area at the time of a subroutine call of a microcomputer to be debugged and a return address written in a storage circuit at the time of the subroutine call. A return address monitoring circuit for a debug device, comprising: a comparison circuit for comparing in real time upon return.