JPH01114945A - Tracing system for data processor - Google Patents

Abstract

PURPOSE:To store only trace information necessary for a tracer memory by providing the title system with a trace start address storing means, an executing instruction address storing means, a comparing means, a gate means, a trace interruption signal output means, etc. CONSTITUTION:In case of storing trace information in the tracer memory 27, a CPU 1 outputs the address of an instruction to be tested as a trace start address 11 and stores the address 11 in the trace start address storing register 21. Then, the CPU 1 executes preparation for the execution of the instruction and stores a software instruction address 12 in a software instruction address storing register 22. When the contents of the register 22 coincide with that of the register 21, the comparator 24 outputs a trace start signal 25 to a gate circuit 26 and the contents of a firmware instruction address storing register 23 are sequentially stored in the memory 27. At the end of the execution of the instruction to be tested, the CPU 1 outputs a trace interruption signal 14 and the value of the register immediately after the execution of the instruction is stored in the memory 27, so that only necessary trace information can be stored in the memory 27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tracing method for a data processing device, and particularly to a tracing method for a data processing device that can trace only necessary trace information.

[Conventional technology]

Conventionally, this type of tracing method detects a trace start address, starts tracing, and then does not stop tracing until the tracer memory becomes full.

[Problem that the invention attempts to solve]

Conventionally, as described above, after starting tracing, tracing was not stopped until the tracer memory was full, which caused a problem in that even unsatisfactory trace information was stored in the tracer memory.

The present invention solves these problems, and its purpose is to allow only necessary trace information to be stored in the tracer memory.

Means for Solving Problem c] In order to solve the above-mentioned problems, the present invention provides a trace method for a data processing device that sequentially executes instructions stored in a memory. trace start address storage means for storing the address of the instruction being executed; execution instruction address storage means for storing the address of the instruction being executed; and the contents of the trace start address storage means and the contents of the execution instruction address storage means match. a comparison means for outputting a trace start signal according to the method; a gate means for controlling whether or not the address of the firmware instruction being executed is traced to the tracer memory; and a gate means for outputting a trace interrupt signal during or immediately after execution of the instruction under test. and a trace interrupt signal output means, wherein the gate means starts tracing when the trace start signal is output, and interrupts the trace when the trace interrupt signal is output.

[For production]

The address of the instruction under test is stored in the trace start address storage means, and the address of the instruction being executed is stored in the execution instruction address storage means.

The comparison means outputs a trace start signal when the instruction under test is executed and the contents of the trace start address storage means match the contents of the currently executed instruction address storage means. When the trace start signal is output, the gate means sequentially stores the address of the firmware instruction being executed in the tracer memory. The trace interrupt signal output means outputs a trace interrupt signal during or immediately after execution of the instruction under test, and the gate means interrupts the trace by outputting the trace interrupt signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a central processing unit (CPU) 1, a trace control unit 2, and a main memory 3 in which instructions executed by the central processing unit 1 are stored. There is.

The trace control unit 2 includes a trace start address storage register 21 that stores a trace start address (address of the instruction under test) 11 from the central processing unit 1;
A software instruction address storage register 22 that stores the software instruction address 12 from the central processing unit 1, a firmware instruction address storage register 23 that stores the firmware instruction address 13 from the central processing unit 1, a comparison circuit 24, a gate circuit 26, and a tracer memory. 27.

FIG. 2 is a flowchart showing an example of processing performed by the central processing unit 1 when storing trace information in the tracer memory 27, and the operation of this embodiment will be described below with reference to each figure.

When storing trace information in the tracer memory 27, the central processing unit 1 first outputs the address of the instruction under test as the trace start address 11 (step 531).

This trace start address 11 is stored in the trace start address storage register 21.

Next, the central processing unit 1 performs preliminary preparations to set up an environment for executing the instruction under test (step 532),
After that, execute the instruction under test (step 333),
After the central processing unit 1 starts the process of step 332, every time the central processing unit 1 executes a software instruction, the software instruction address 12 indicating the address of the software instruction being executed is
is added to the software instruction address storage register 22,
Every time a firmware instruction is executed, a firmware instruction address 13 indicating the address of the firmware instruction being executed is added to a firmware instruction address storage register 23.

When the contents of the software instruction address storage register 22 and the contents of the trace start address storage register 21 match, that is, when the instruction under test is executed, the comparison circuit 24 detects
A trace start signal 25 is output.

When the trace start signal 25 is output, the gate circuit 26
is opened and the firmware instruction address storage register 23
The contents of are sequentially stored in the tracer memory 27.

When the execution of the instruction under test is completed, the central processing unit 1 performs post-processing (step 534). In step S34, the central processing unit 1 performs post-processing that is necessary to confirm the normality of the execution result of the instruction under test. A subroutine call is made to save the register value in the storage device immediately after the test instruction is executed. This subroutine call is a monitor call using a trap, and when the central processing unit 1 detects a trap, it outputs a trace interruption signal 14. do. However, the purpose of the execution of the test instruction is to detect program errors, and if a program error is detected during the execution of the instruction under test, a trap will occur during the execution of the instruction under test, so the central processing unit 1 Before making the call, a trace interrupt signal 14 is output, and then a subroutine call is made. When the trace interrupt signal 14 is output, the gate circuit 26 is closed and tracing is interrupted until the next trace start signal 25 becomes valid.

〔Effect of the invention〕

As described above, the present invention provides a comparison means that outputs a trace start signal when a trace start address matches the address of an instruction being executed, and a comparison means that outputs a trace stop signal during or immediately after execution of the instruction under test. A trace interrupt signal output means is provided to trace the address of the firmware instruction executed between the output of the trace start signal and the output of the trace interrupt signal. This has the advantage that only trace information can be stored in the tracer memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart showing an example of processing of the central processing unit 1 when storing trace information in the tracer memory 27. In the figure, 1...Central processing unit, 2...Trace control unit, 3...Main storage device, 21...Trace start address storage register, 22...Software instruction address storage register, 23 ... Firmware instruction address storage register, 24... Comparison circuit, 26...
Gate circuit, 27... tracer memory.

Claims (1)

[Claims] In a tracing method for a data processing device that sequentially executes instructions stored in a memory, there is provided a trace start address storage means for storing an address of an instruction under test, and an address of an instruction being executed. a comparison means for outputting a trace start signal when the contents of the trace start address storage means match the contents of the execution instruction address storage means; Gate means for controlling whether or not to trace an address to a tracer memory; and trace interrupt signal output means for outputting a trace interrupt signal during or immediately after execution of the instruction under test; A tracing method for a data processing device, characterized in that tracing is started when a signal is output, and tracing is interrupted when the trace interruption signal is output.