JPS63143636A - Break point controller - Google Patents

Abstract

PURPOSE:To efficiently attain the developing work of software by setting up a break point by means of a software using a memory. CONSTITUTION:Prior to the execution of a debugged program, a break point is previously stored in a memory 14. The addresses of the memory 14 correspond to the execution addresses of a program and the existence of execution stop and the comment of the break point are stored in all execution areas correspondingly to each instruction. Thereby, a flag is set up in an interruption bit 18 of an execution address to be stopped at its execution and the comment of the break point is entered in a break point entering bit 19. At the time of executing the program, a break point control device refers the contents of the memory 14 every time a CPU fetches an instruction. When the flag of the interruption bit 18 is detected, the CPU starts interruption processing, reads the break point type entering bit 19 and is turned to a break state.

Description

[Detailed description of the invention] [Industrial application field] This invention was made at the software development stage.

This invention relates to a breakpoint control device that can set very specific program stop points (breakpoints) when a program to be debugged is executed.

The operation check (debugging) of the developed program is performed by dividing the program into several stages in order to easily detect defective parts of the program and check the operation of the program counter, etc. Therefore, a breakpoint control device is required to control the point at which execution of the program is stopped.

[Conventional technology]

FIG. 5 shows an example of a conventionally used breakpoint control circuit. In the figure, OI is the emulator bus, e2L @, 64. QL @uo P U(O
These are registers that can interface with the internal processing unit (processing unit) bus (8) and are individually assigned υ addresses. Punishment, (a), (21,
(to), ((+1 is a comparator that compares two inputs,
03 is an OR circuit.

In FIG. 5, registers E, 03), 124), (c),
Store any execution stop factor in @. For example, it is conceivable to designate the desired breakpoint execution address and the next execution address of register (to) K16 in the register, and to designate any command such as a write command as a breakpoint in the register (to).

The communication register 02 shown in FIG. 5 includes a comparator and a register (
C) is the comparator and register c! 4 is the comparator -, register (C) is the comparator (to), and register (A) is the comparator C3.
There are 11 sets each. When the program to be depacked is executed, signals such as execution addresses and commands on the escalator bus ae are sent to the comparators -, @, (2L [with]
Input to On and register first, (c), (goods), (to)
, is successively compared with the data set in (a). Comparator
, +28).

c2! I, (to), 01) comparison result is OR circuit O3
The logical sum is calculated by p, and when a breakpoint is detected, a request to stop the execution of the program to be debugged is output to the calculation processing section. When the calculation processing unit receives the execution stop request, it stops the execution of the program while maintaining the current state.

Since the conventional breakpoint control device is configured as described above, the number of breakpoints cannot be set to a value that is too large for the number of registers.

[Problem that the invention seeks to solve]

The number of breakpoints that can be set in a conventional breakpoint controller is proportional to the number of registers and comparators. Therefore, when attempting to set a large number of breakpoints, there is a problem in that the number of registers and comparators increases proportionally.

Also, if the breakpoint control device detects a breakpoint and sends an interrupt signal to OPH, the CPU
had the problem that it was not possible to determine the meaning or type of the breakpoint corresponding to the interrupt signal.

This invention was made to solve these problems, and even if a large number of breakpoints are set, it can still function without making the circuit larger or more complicated. It is an object of the present invention to provide a breakpoint control device that can send a breakpoint type signal together with an interrupt signal to an OPU when a breakpoint is detected.

The breakpoint control device according to the invention includes software control means, data interface means with ap'a, breakpoint condition determination means, and breakpoint type determination means. It was established.

[Effect]

In this invention, breakpoints and breakpoint types are stored in memory in advance, and when a program is executed, the contents of the memory are successively referenced to control CPH interrupts when a breakpoint is detected.

〔Example〕

FIG. 1 is an overall configuration diagram of an embodiment of a breakpoint control device according to the present invention. As is clear from FIG.
A breakpoint control device (3) is connected to the PU bus (8) and is an interface means IJ /d A means for interfacing or monitoring the breakpoint control device (3) with the CPU bus (8). Point setting means + 5) Memorize the position and conditions of Fi breakpoints,
The breakpoint type setting means 16) stores the meaning and reason of the breakpoint as a comment.The breakpoint setting means (5) and the breakpoint type setting means (61) are realized by a large-capacity storage device such as memory. When the above settings are completed and the debugged program is executed, the breakpoint determination means +71 [OPU
Based on the emulation information of the bus 18), refer to the contents stored in the breakpoint setting means (5), and when a breakpoint is detected, the execution stop request signal (9) is opened.
U (1+).

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 to 4. FIG. 2 shows the circuit configuration of the breakpoint control device (3), and FIG. 3 shows the memory formant along memory 0. Also shown in FIG. 4 is an operational flowchart of the breakpoint control device.

Before executing the program to be debugged, store a breakpoint in memory 04). The address in Memo January 14 corresponds to the execution address of the above program, and executes one instruction at a time for all execution areas. At the execution address where you want to memorize the presence or absence of a stop and the breakpoint comment, and therefore want to stop execution, set a flag in interrupt bit Q81 shown in FIG. When the above program is executed each time the above program is executed, the breakpoint control device directly writes the interrupt pin 081rri, which refers to the contents of the memo IJ (141), every time o P U fil fetches an instruction. Since it is connected to the interrupt input terminal of OPH, when the flag of 9 interrupt pin 08 is detected, 0PUflll starts interrupt processing, reads the breakpoint type entry bit 09 of memory (141), and enters the break state.The program is executed again. The same operation as above is repeated until the end of the program. The content explained above is shown in the flowchart in Figure 4. Step 8, 0 is a period for setting breakpoints in memory (14). Execution of the program begins at step C.

In step d, it is determined whether the actual row address is a breakpoint. If it is not a breakpoint, execute the 9th execution address. O if it is a breakpoint
An interrupt request is made to the PH in step θ, and the memory (+4
1 to read the break point type entry pit a9 in step f, and break in step g. When program execution starts again, the next execution address is executed.

Such operations are monitored in step h until the end of the program.

〔Effect of the invention〕

As described above, according to the present invention, breakpoint settings, which were handled by conventional hardware, are now handled by software using memory, so many breakpoints can be set without complicating the circuit. I can do it again.

Since the characteristics of breakpoints can be fully determined, software development work can be carried out efficiently.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of the first part of the breakpoint control device according to the present invention, FIG. 2 is a configuration diagram of the main body of the breakpoint control device, FIG. 3 is a diagram showing the format of the memory that is a component of the device, and FIG. FIG. 4 is an operational flowchart of the present invention, and FIG. 5 is a circuit diagram of a conventional breakpoint control device. In the figure, +13 [OPU, +31 is a breakpoint control device, 18) is an OPU bus, and (9) is an execution stop request signal. a■ is the emulator bus, αB is the address bus, α2F
The i data bus, aS, is an interface circuit. In addition, the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] In program debugging work performed during software development, there is a storage unit that sets and stores breakpoints and breakpoint states for the computer processing unit that executes the program, and a storage unit that stores the breakpoint status at the program execution stage. a breakpoint determination means that determines based on the contents of the storage section and outputs a program execution stop request signal to the computer processing section when the breakpoint is reached; the computer processing section, the storage section, and the computer processing section; and interface means for exchanging information with the breakpoint determining means.