JPS6211745B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprocessor, particularly a one-chip
This invention relates to a microcomputer step system that allows the internal state of a microprocessor to be read.

Traditionally, the internal registers of a single-chip microprocessor, such as the accumulator and index
The status of registers, stack pointers, and condition code registers could not be monitored during program execution. It is also performed when debugging a program or checking for failures. In the method of stopping microprocessor processing by stepping through the program for each instruction, only the execution address of the instruction is monitored, making it difficult to grasp the state of internal registers, which can lead to failures or problems between tests. It was causing a problem.

The present invention is based on the above considerations, and includes:
It is an object of the present invention to provide a microcomputer stepping method that allows the execution address of an instruction and the state of an internal register to be read when the microprocessor steps an instruction. Therefore, the microcomputer step system of the present invention includes a microprocessor and a control memory, stores the internal state of the microprocessor in a predetermined area of the control memory when an address match interrupt is received, and then A microcomputer configured to stop itself, change the set address for address matching after being put into an operating state, and return to a normal state from an interrupt state;
an address match detection unit that compares the set address and the execution address of the microcomputer and sends an interrupt signal to the microprocessor when the two match; The microcomputer is characterized by comprising an adapter that reads and sends the data to another processing device and puts the microcomputer into operation after the reading is completed, and another processing device that displays the data sent from the adapter. It is something. below,
The present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing a hardware configuration of one embodiment of the present invention, FIG. 2 is a diagram showing one embodiment of an address match detection section, and FIG. 3 is a diagram showing a program configuration in the present invention.

In the figure, 1 is a microprocessor, 2 is a control memory, 3 is an adapter, 4 is an address match detector, 5 is a bus including an address bus and a data bus, 6 is a control line, 7 is a setting address register, Reference numeral 8 indicates an address comparison circuit, and reference numeral 9 indicates an interrupt circuit. The control memory 2 is composed of a RAM, in which various programs are stored. Further, when an interrupt is accepted, the instruction execution address of the microprocessor 1 and the status of internal registers (amount radar, index register, stack pointer, condition code register) are stored in a predetermined area of the control memory. When the adapter 3 detects that the hold signal is turned on, it reads the data in the predetermined area of the control memory and sends it to the service processor SVP (not shown), and after reading the data, it outputs the hold signal. Release. As shown in FIG. 2, the address match detection unit 4 includes a set address register, an address comparison circuit that compares the contents of the set address register and the address on the address bus, and when the address comparison circuit 8 outputs a match. The interrupt circuit 9 includes an interrupt circuit 9 that sends an interrupt signal to the microprocessor 1. The contents of setting address register 7 are
Rewritten by.

FIG. 3 shows the configuration of a program in the present invention. The step processing routine is executed when an interrupt signal from the interrupt circuit 9 is accepted, and includes a series of instructions for stacking the internal state of the microprocessor 1 in a predetermined area of the control memory 2 and a hold signal turned on. and an instruction to
It has an instruction to set the next address in the setting address register 7 and a return instruction.

Next, examples of the present invention will be described. Now in Figure 3
Assume that an address corresponding to an LDA (load accumulation radar) instruction is set in the setting address register 7. When the LDA instruction is executed,
Interrupt circuit 9 sends out an interrupt signal. When this address match interrupt is accepted, execution of the step processing routine is started. By executing this step processing routine, the internal state of the microprocessor 1 is saved in a predetermined area of the control memory 2, and then the microprocessor is stopped and the halt signal is made active. When the hold signal becomes active, adapter 3
reads the internal state information of the microprocessor 1 stored in a predetermined area of the control memory, sends it to the service processor SVP, and the service processor SVP displays it. The device shown in FIG. 1 constitutes a part of an input/output control device. The adapter 2 reads all data in a predetermined area of the control memory 2, sends it to the service processor SVP, and then sets the halt signal to a non-active value. As a result, execution of the step processing routine is restarted, the next address, for example, an address incremented by 1, is set in the setting address register 7, and a return instruction is then issued. This return instruction returns to the normal execution routine and returns to the instruction at the next address (in the example shown).
STA instruction) is executed. When the address of the STA instruction matches the contents of the configuration address register,
The step processing routine is executed again.

As is clear from the above description, according to the present invention, it is possible to grasp the execution address and the state of each internal register for each step.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a hardware configuration of one embodiment of the present invention, FIG. 2 is a diagram showing one embodiment of an address match detection section, and FIG. 3 is a diagram showing a program configuration in the present invention. 1...Microprocessor, 2...Control memory,
3...Adapter, 4...Address match detection section, 5
〓〓〓〓〓
...Bus including address bus and data bus, 6...Control line, 7...Setting address register, 8...Address comparison circuit, 9...Interrupt circuit. 〓〓〓〓〓

Claims (1)

[Scope of Claims] 1. A microprocessor comprising a microprocessor and a control memory, and upon receiving an address match interrupt, stores the internal state of the microprocessor in a predetermined area of the control memory, and then stops itself; A microcomputer configured to return from an interrupt state to a normal state by changing the set address for address matching after being put into an operating state, and comparing the set address with the execution address of the above microcomputer and determining whether the two match. an address match detection unit that sends an interrupt signal to the microprocessor when the microcomputer stops; and an address match detection unit that reads data in a predetermined area of the control memory and sends it to another processing device when the microcomputer stops; A step system for a microcomputer characterized by comprising an adapter for putting the computer into operation and another processing device for displaying data sent from the adapter.