JPS6091458A - Program debug device of microprocessor - Google Patents

Abstract

PURPOSE:To inspect easily the using state of a program at the actual working place of a debug device by comparing the address of information read out of a read-only fixed memory with a specific address. CONSTITUTION:A specific address with which the discontinuation of execution is desired is set to a register circuit 4 from a test console 6. Then an execution start command is applied from the console 6. In this case, the address of information is latched to an address latch circuit 2 every time said information is read out of an ROM by a CPU1. If the information is equal to an ''instruction'', the corresponding address is delivered to a comparator 5 by an instruction fetch detecting circuit 3. The comparator 5 outputs an instruction signal to the CPU1 when the coincidence is obtained between the address set at the circuit 4 and the address supplied from the circuit 3. Then the CPU1 discontinues its execution by said interruption signal and outputs an address, etc. to the console 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a program debugging device for a microprocessor that debugs a program written in a reprint-only fixed storage device.

(b) Background of the Technology Recently, with the development of integrated circuit technology, many devices have appeared that use microprocessors (hereinafter abbreviated as MPUs) to control devices by software. The programs used in these applications are often written in fixed storage devices (hereinafter referred to as ROMs) due to the processing speed and storage format of the programs, i.e., the stored programs are not erased even when the power is turned on and off. .

However, the programs used are not necessarily perfect, and problems may occur only when specific usage conditions are met during actual use. Sometimes you may want to quickly determine the cause by looking at the contents of the program being used.
In the case of a ROM that cannot be written to, it is not possible to stop the execution of a program at a specific point, or to re-execute it and view the contents without a specific device.

In order to facilitate the maintenance work of equipment using MPU equipped with ROM, and also to facilitate the debugging work of programs written in ROM.

It is desired to develop a program debugging device that can easily stop and rerun a program at a specific point without special equipment.

(C) Prior Art and Problems When debugging an MPII program, it may be desirable to stop execution of the program to be debugged at a specific instruction address and refer to the contents of the storage device.

If the program is written to data-writable random access memory (hereinafter referred to as RAM), you should debug it by changing the instruction at the address you want to stop to an interrupt instruction and executing that interrupt instruction. Program execution can be stopped.

However, if you want to use it in a place where you want to be able to freely turn off the power, it is necessary to use a ROM whose stored information will not be lost forever, but since the contents written in the ROM cannot be rewritten, it is not possible to write to the ROM. When debugging a program, either debug the program in RAM and write the final program to ROM, or use a specific device that is inconvenient to carry (for example, an in-circuit emulator that has a dedicated MPTL and displays the program contents on a display with a keyboard). ) to debug the program.

However, if you want to quickly and easily find a defective part of a program under actual operating conditions, there is a problem in that it cannot be done immediately.

(d) Purpose of the Invention The object of the present invention is to provide a new MP[I program debugging device that solves the above-mentioned problems.
The usage status of the program can be easily verified at the actual operating location of the device by using the function built into the existing hardware of the device equipped with ROM, without connecting the program written in the OM to a specific device. The object of the present invention is to realize a program debugging device capable of l'lPυ.

(8) Structure of the Invention The present invention provides a microprocessor in which a program to be executed is written in a fixed storage device for continuous use only, and a microprocessor is used to read and control the program to be executed written in the fixed storage device for continuous use only. In the apparatus comprising: debugging a program written in the reprintable fixed storage device;

means for setting a specific address at which execution of the program is stopped or re-executed, and an address of the read information each time the microprocessor reads the information written in the reprint-only fixed storage device; and means for comparing the output information of the means for setting the specific address and the output information of the means for latching the address of the read information, and the program is written in the fixed storage device for continuous use. M characterized in that the usage state of the program can be verified i** at the actual operating location by a function built into the existing hardware of the device.
This can be achieved using the PIJ program debugging method.

(f) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 shows one embodiment of the apparatus according to the present invention, and FIG. 2 shows the operating sequence of another embodiment.

In the figure, 1 is a central processing unit (hereinafter abbreviated as CPII), 2 is an address latch circuit, 3 is an instruction fetch detection circuit, 4 is a register circuit, 5 is a comparator circuit, and 6 is a test console.

In this embodiment, the CPIII controls the operation of the entire device (not shown) by a program, and the CPIII is a ROM.
2. Address latch circuit (not shown) that stores the address of information retrieved from a source until the next information is retrieved. From the address stored in the address launch circuit 2 to the CPU
An instruction fetch detection circuit 3 that detects that I has fetched an "instruction" from a ROM (not shown) and outputs the address of the fetched "instruction" to the comparator circuit 5. C.P.II.
4. A register circuit that sets the address at which you want to stop I (referred to as a break address). Instruction fetch detection circuit 3
Comparator circuit 5 which compares the output address with the break address set in the register circuit 4 and outputs a signal when they match. Connect to a device (not shown) and use the CPU
The test console 6 is configured to input various test commands to perform a functional test of the device (not shown).

Note that the address latch circuit 2. Instruction function detection circuit 3. Register circuit 4. It is assumed that the comparator circuit 5 is initially implemented in the device (not shown).

Further, the test console 6 is designed to be portable and easily portable, as it is not normally connected and is connected only during the function test I.

Next, the operation of this embodiment will be explained in order of operation steps.

[Step 1]: Set a specific address at which you want to stop execution in the register circuit 4 from the test console 6.

[Step 2]: Input an execution start command from the test console 6. At this time, each time the CPUI reads information from the ROM, the address is latched into the address latch circuit 2. If the information is an "instruction", it is determined by the instruction fetch detection circuit 3.

The address is output to comparator circuit 5.

[Step 3]; When the address set in the register circuit 4 and the address input from the instruction fetch detection circuit 3 match, the comparator circuit 5 outputs an interrupt signal to the CPUI.

(Step 4): The CPU 1 outputs the address, etc. whose execution was stopped to the test console 6 in response to an interrupt signal from the comparator circuit 5.

[Step 5] Return to [Step 1] by secondary operation.

Next, as another example, consider the ROM (
Example of writing the same processing program as the above example into a part of the RAM (not shown) used for other purposes in the MPII (not shown) I will explain about it.

The operation of this embodiment utilizes the single step operation (an interrupt occurs every time one instruction is executed) of the MPII (not shown) as shown in FIG.

[Step 1]: Connect the test I console 6 to the equipment W (not shown) and connect the test console 6 to the RO.
Enter the stop command for M (not shown) and press R.
OM (not shown) Switch to test mode.

[Step 2]: Store the break address in RAM (not shown) from the test console 6.

[Step 3]: Put the MPU (not shown) into single-step operation.

[Step 4]: Execute one instruction of the program to be debugged.

[Step 5]: Single step interrupt processing.

[Step 6]: Enter the address of the "instruction" that processed the interrupt.

[Step 7]: The address of the "instruction" processed by the interrupt is compared with the break address stored in the RAM (not shown) in the MPU (not shown).

If the comparison results in the MPU (not shown) match, the contents of the "instruction" stored at that time are transferred to the test console 6.
to be displayed in the display area.

[Step 8]: If the comparison result in [Step 7] does not match, MP[I (not shown) is made to operate in a single step again.

[Step 9]; Return to [Step 4] and repeat until they match.

As described above, the present invention does not require any additional hardware.
It can also be implemented by adding a program to a part of existing hardware.

(g) Effects of the Invention According to the present invention, there is provided an MPLI program debugging device that can debug even a program written in a ROM using normally used equipment and hardware attached to the equipment. It has the effect of being able to provide the following.

[Brief explanation of the drawing]

FIG. 1 shows one embodiment of the apparatus according to the present invention, and FIG. 2 shows the operating sequence of another embodiment. In the figure, 1 is a CPU, 2 is an address latch circuit, and 3 is a CPU.
Reference numeral 4 indicates an instruction fetch detection circuit, 4 a register circuit, 5 a comparator circuit, and 6 a test console. 1 Guo 1 diagram

Claims (1)

[Claims] A program to be executed is written in a continuous-only fixed storage device, and the apparatus comprises a microprocessor for reading and controlling the program to be executed written in the continuous-only fixed storage device, In order to debug a program written in a storage device, means for specifying a specific address at which execution of the program is stopped or re-executed; Each time the stored information is read, means for latching the address of the read information; and means for comparing the output information of the means for setting the specific address with the output information of the means for latching the address of the read information. A microprocessor program debugging device characterized by comprising: