JPH05189267A - Operation control system for microprocessor and emulator - Google Patents

Abstract

PURPOSE:To make the intervention of software in break factor analysis unnecessary so as to attain the high speed of break processing by generating an exceptional processing address by a vector generation circuit in accordance with a break factor at that time, and making a re-start address after exceptional processing different for each break factor. CONSTITUTION:An emulator is coupled to a target system through an interface cable and an IC socket 39 connected to it. A microprocessor 31 is provided with the input terminal of a NMI signal 12. The microprocessor 31, an emulation control part 33, a memory 34, a break detection circuit 35, a trace memory 36, an emulation memory 37, and a user interface 38, etc., are connected respectively to an emulation bus 32. Then by making the re-start address after the exceptional processing different for each break factor, the intervention of the software in the break factor analysis is made unnecessary, and thus, the high speed of the break processing can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of controlling the operation of a microprocessor, and more particularly to a control technique for switching the operating state of the microprocessor by using exception processing such as an interrupt or interrupt instruction. The present invention relates to a technique effective when applied to an emulator that enables development support of software operating on a target system by causing a microprocessor to execute a targeted target program.

[0002]

2. Description of the Related Art In developing a microprocessor (microcomputer) application device, an emulator is used to debug the application system and perform detailed evaluation of the system. For example, an emulator is a system development device such as a parent computer for software development,
It is connected to the target system under development and acts as a debugger while acting as a function of the microprocessor (target microprocessor) included in the target system, and supports detailed system debugging. In such an emulator, the tip of the cable extended from the main body can be coupled to the target system through a plug such as an IC socket, and further various data and status signals are sampled in real time during execution of emulation. , And various debug functions such as a real-time trace function for storing it in the trace memory unit and a break function for substantially stopping the emulation operation.

Generally, an emulator executes a return instruction and reads a return address from the contents of the stack to execute a user program from an arbitrary address. A break is performed by changing the flow of execution to a user program by inputting an interrupt or executing an interrupt instruction. In other words, in the conventional break method, the operating space of the microprocessor is switched from the user program execution state to the emulator control state before stacking due to interrupt input or exception handling of interrupt instruction execution, and when the break occurs, the break factor is set in the emulator status register. The information shown is set and the break factor of the status register is analyzed by the emulator control program from the restart address.

As an example of a document describing the operation of such an emulator, "All About Microcomputer Development (Pages 78 to 95)" issued by Denpa Shimbun on June 20, 1989. There is.

[0005]

As described above, the operating space of the microprocessor is switched from the user program execution state to the emulator control state before stacking due to exception input of interrupt input or interrupt instruction execution, and the emulator status is generated when a break occurs. In the conventional method of setting break factor information in the register and analyzing the break factor of the status register by the emulator control program from the restart address, the processing speed of the microprocessor is improved and the function is enhanced by mounting peripheral functions. As the control of emulation using such a processor becomes more and more complicated, it is difficult to speed up break processing.

An object of the present invention is to speed up break processing.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the exception processing address when the microprocessor fetches the contents of the exception processing address is generated by the hardware according to the break factor at that time, and the restart address after the exception processing is generated for each break factor. It is intended to be different.

Further, by generating a break detection circuit for detecting a break factor and the exception processing address when the microprocessor fetches the exception processing address, based on the detection result of the break detection circuit, The emulator is configured to include a vector generation circuit for making the restart address after the exception handling different for each break factor.

[0011]

According to the above means, the exception processing address when the microprocessor fetches the contents of the exception processing address is generated by the hardware according to the break factor at that time, and the restart is performed after the exception processing. Making the address different for each break factor eliminates the need for software intervention in the break factor analysis, which achieves a faster break process.

[0012]

FIG. 1 shows the overall configuration of an emulator according to an embodiment of the present invention.

The emulator shown in FIG. 1 is connected between a system development device such as a parent computer for software development and a target system under development, and is connected to a microprocessor (target microprocessor) included in the target system. It has a function as a debugger while substituting for functions, and supports detailed system debugging. Such an emulator, via the interface cable and IC socket 39 connected to it,
A real-time trace function that is connected to the target system and samples various data and status signals in real time during execution of emulation and stores them in the trace memory 36, etc. It has various debug functions such as a break function to stop.

A microprocessor (MPU) 31 equivalent to a target microprocessor mounted in a target system (not shown) has an input terminal for an NMI (non-maskable interrupt) signal 12. The emulation bus 32 includes an emulation controller 33 for switching a predetermined state of the target microprocessor 31 when the microprocessor 31 acts as a target microprocessor, a memory 34 used for controlling the emulation operation, and a microprocessor 31. Break detection circuit 35 for detecting the cause of execution stop of the user program by monitoring the control state of the emulation bus 32 and the state of the emulation bus 32, and a trace memory for sequentially tracing and storing the address, data and control signal given to the emulation bus 32. 36, an emulation memory 37 for substituting a data memory or a program memory to be included in the target system, and a user interface for coupling with a target system (not shown) Part 38 is coupled, respectively. The NMI signal 12
Is asserted when the break detection circuit 35 detects that the break condition is satisfied. The emulation control unit 33, the memory 34, the break detection circuit 3
5, the trace memory 36 and the emulation memory 37 are controlled by the host CPU (central processing unit) 14 through the system bus 13. A system memory 15 and an I / O interface unit 16 are coupled to the system bus 13, and a disk device having a disk 17 as a recording medium and a parent computer including a CRT display 18 are connected via the I / O interface unit 16. Be combined.

Generally, in an emulator, the operating space of the microprocessor is switched from the user program execution state to the emulator control state before stacking due to interrupt input or interrupt instruction execution exception processing, and when a break occurs, information indicating the break factor in the emulator status register is displayed. Is set and the break factor of the status register is analyzed by the emulator control program from the restart address.However, in the emulator of this embodiment, in order to speed up break processing,
By generating the exception processing address when the microprocessor 31 fetches the exception processing address based on the detection result of the break detection circuit 35,
It includes a vector generation circuit 40 for making the restart address after the exception processing different for each break factor.

FIG. 2 shows a configuration example of the vector generation circuit 40, and FIG. 3 shows a restart address map for each break factor.

As shown in FIG. 2, the microprocessor 31 in this embodiment is not particularly limited, but 16
An address bus 19 having a bit configuration (A15 to A0),
It is coupled to the data bus 20 having an 8-bit structure (D7 to D0). The NMI vector table address of the microprocessor 31 is H'0080 (00 in binary display).
00000010000000), and the restart address (equal to the program counter PC value and set to 2 bytes) is set in the vector table. The emulation activation is performed by a return interrupt instruction, and the break processing is performed by asserting NMI. The emulation bus 32 controls the emulation operation from the fetch of a new program counter value by a return interrupt instruction to immediately before the stack of an NMI interrupt exception due to a break as user space. Further, in this embodiment, although not particularly limited, three types of break factors different from each other are set. Let them be break factor 1, break factor 2, and break factor 3.

The vector generation circuit 40 includes two comparators 2 for monitoring the address of the address bus 19.
1 and 22, negative logic AND gates G1 and G2, an inverter G3, and two output buffers 2 activated by the output states of the negative logic AND gates G1 and G2.
3 and 24 are included. The comparators 21 and 22 are 2
The system has a group of input terminals, that is, input terminals A7 to A0 and input terminals B7 to B0. In the comparator 21, the addresses A15 to A8 of the address bus 19 are transmitted to the input terminals A7 to A0, and the input terminals B7 to B0 are fixed to the low level (ground level). When the switching USER signal 11 is asserted to a low level, the states of the input terminals of the two systems are compared with being enabled. If both input logic states are equal in this comparison, the comparator 2
The output terminal of 1 is set to low level. Such a state is transmitted to the input terminal A0 of the comparator 22. In the comparator 22, the addresses A7 to A1 of the address bus 19 are transmitted to the input terminals A7 to A1 and the input terminal B7 is at a high level (Vcc level).
Therefore, the input terminals B6 to B0 are fixed to the low level. When the read control signal / READ (/ indicates that the signal is low active) is asserted to the low level, the comparator 22 is enabled and the comparison output of the comparator 22 is the negative logic AND gate G1 in the subsequent stage. , G2. With such a configuration, by monitoring the state of the address bus 19, it is possible to detect the NMI interrupt vector table address H'0080 of the microprocessor 31 as shown in FIG.

An output buffer 23 and an output buffer 24, which are activated depending on the output state of the negative logic AND gates G1 and G2, are arranged at the subsequent stage. The input terminals 7 to 1 of the output buffer 23 are fixed to low level, and the input terminal 0 is fixed to high level. Output terminals are D7 to D
8 bits of 0, which are coupled to the data bus 20. The input terminals 7, 3, 2, 1, 0 of the output buffer 24 are fixed to a low level so that the break factor signals 3, 2, 1 from the break detection circuit 35 are transmitted to the input terminals 6, 5, 4. Is becoming The output terminal of the output buffer 24 is also 8 bits like the output buffer 23,
It is coupled to the data bus 20. The address A0 of the address bus 19 is transmitted to the negative logic AND gate G1 and the negative logic AND gate G2 via the inverter G3, and the negative logic AND gates G1 and G2 are changed depending on the state of the address A0. It is activated complementarily. As a result, the output buffer 23 and the output buffer 2
4 are complementarily enabled, and different restart addresses for each break factor are output to the data bus 20 in accordance with even and odd addresses.

Break detection circuit 3 during emulation
When it is detected that the break condition is satisfied by 5, the break detection circuit 35 asserts the NMI signal 12. After that, the emulation control unit 33 causes the NMI
When the stack cycle of the interrupt exception is detected, it becomes the emulation control space and the space switching USER signal 1
When 1 is asserted, the vector generation circuit 40 is made operable.

In the vector generation circuit 40, the address bus 1
The state of 9 is monitored by the comparators 21 and 22. In this monitoring, a read cycle to the NMI interrupt vector table address H'0080 is detected (note that since the vector table is a word size, the monitoring of the address A0 is unnecessary). ). When this read cycle is detected, the output state of the comparator 22 is asserted to the low level, thereby activating the negative logic AND gates G1 and G2. At this time, the address bus 19
Logic AND gate G1 according to the state of address A0 of
Alternatively, the output of G2 is asserted to the low level, whereby the output buffer 23 or the output buffer 24 is enabled. When the output buffer 23 is enabled, the upper 8 bits of the restart address are formed, and when the output buffer 24 is enabled, the lower 8 bits of the address are formed. The fourth bit of the input terminals 0 to 7 of the output buffer 24,
The signals of break factors 1, 2, and 3 from the break detection circuit 35 are input to the 5th and 6th bits, and the restart address can be switched even if a plurality of break factors occur. It is said that. The restart address thus generated according to the break factor is fetched by the microprocessor 31 via the data bus 20. In order to prevent the restart address output to the data bus 20 from being destroyed, during the period in which the output buffer 23 and the output buffer 24 are enabled,
All buffers (not shown) coupled to the data bus 20 are in a high impedance state.

According to the above embodiment, the following operational effects can be obtained.

(1) When the microprocessor 31 fetches the contents of the exception processing address, the exception processing address is generated by the vector generation circuit 40 according to the break factor at that time, and the restart address after the exception processing is performed. By differentiating each of the break factors, software intervention in the break factor analysis is not required, so that the break processing can be speeded up.

(2) Based on the detection result of the break detection circuit 35, the break detection circuit 35 for detecting the break factor and the exception processing address when the microprocessor fetches the exception processing address are determined. By configuring the emulator by including the vector generation circuit 40 for making the restart address after the exception handling different for each break factor, software intervention in the break factor analysis is unnecessary in the emulator. Therefore, it is possible to shorten the time required for system debugging by speeding up the break processing and further speeding up the break processing.

(3) In the conventional break method, the operating space of the microprocessor is switched from the user program execution state to the emulator control state before stacking due to interrupt input or exception processing of interrupt instruction execution, and the emulator status register is generated when a break occurs. Although the information indicating the break factor is set in the above, since the software intervention in the break factor analysis is unnecessary in the above embodiment, the status register for setting the information indicating the break factor is unnecessary. It

Although the invention made by the present inventor has been concretely described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the address bus 19
16 has a 16-bit configuration and the data bus 20 has an 8-bit configuration. However, the configuration is not limited to this, and a 32-bit configuration, for example, is also possible.
Further, in the restart address generation by the vector generation circuit 40, the break factors may be prioritized and the one having the highest priority may be taken into the output buffer 24. Further, even if the emulation processor is provided with a plurality of interrupt terminals so as to correspond to a plurality of types of break factors and the interrupt signal to the processor is asserted via the interrupt terminals different for each break factor, The same effect as can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to an emulator which is a field of use which is the background of the invention has been described, but the present invention is not limited thereto, and the program to be debugged is not limited thereto. It can be widely applied to various debug systems that enable system debugging.

The present invention can be applied on the condition that at least exception processing is used to switch the operating state of the microprocessor.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the exception processing address when the microprocessor fetches the contents of the exception processing address is generated by the hardware according to the break factor at that time, and the restart address after the exception processing is generated for each break factor. The software intervention in the break factor analysis is unnecessary by making the difference between the two, and thereby the break processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an emulator that is an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a main part of the emulator.

FIG. 3 is an explanatory diagram of restart addresses for each break factor in the emulator.

[Explanation of symbols]

 11 space switching USER signal 12 NMI interrupt signal 13 system bus 14 host CPU 15 system memory 16 I / O interface section 17 disk 18 CRT display 19 address bus 20 data bus 21 comparator 22 comparator 23 output buffer 24 output buffer 31 microprocessor 32 emulation Bus 33 Emulation control unit 34 Memory 35 Break detection circuit 36 Trace memory 37 Emulation memory 38 User interface unit 39 IC socket 40 Vector generation circuit

Claims (3)

[Claims] 1. An operation control method of a microprocessor which is moved from a user space to a system space when a break condition is satisfied and is operated so as to fetch a restart address from a vector area, wherein the microprocessor fetches an exception processing address. An operation control method of a microprocessor, characterized in that the exception processing address at the time of occurrence is generated by hardware according to the break factor at that time, and the restart address after the exception processing is made different for each break factor. .. 2. The microprocessor comprises an interrupt input,
Alternatively, the processor operation control system according to claim 1, wherein the exception processing address is fetched after executing an interrupt instruction. 3. A break detection circuit for detecting a break factor in an emulator capable of supporting development of software operating on a target system by causing a microprocessor to execute a target program to be software-debugged. By generating the exception handling address when the microprocessor fetches the contents of the exception handling address based on the detection result of the break detection circuit, the restart address after the exception handling is different for each break factor. An emulator including a vector generating circuit for causing the emulator.