JPS5968034A - Input and output port simulator for microcomputer developing device - Google Patents

Abstract

PURPOSE:To debug efficiently a program by simulating input and output to and from all input and output ports considered as objects of a CPU for developing a program. CONSTITUTION:When a freshly generated program is debugged, an operator connects a simulator 1 to the CPU signal line S of a developing device 2 and puts the CPU5 of the device 2 in operation on the basis of the program to be debugged. When an instruction is an output instruction, output data is read by a data display part 7 and the program is debugged while the output data is compared with a list, etc., to decide on whether the output data is equal to a specific value or not. When the instruction is an input instruction, specific input data is set in a data input part 9 and the instruction execution of the CPU5 is restarted with an operation switch 11. Consequently, a malfunction occurring in the operation is analyzed to debug the program.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output boat simulator for a microcomputer 1iF1 generator.

Various systems that apply microcomputers are:
・-Development usually involves the production of hardware (i.e., actual equipment), the creation of software (i.e., the creation of programs that allow the actual equipment to operate smoothly), and the work of discovering, correcting, and removing defects, i.e., debugging work, etc. be. Among such microcomputer application systems, Zoro l in a system equipped with a real-time input/output device
Depatch work for a RAM machine is often carried out by connecting the actual machine and microcomputer development equipment using an in-circuit emulator once the prototype of the actual machine has been completed. For this reason, if there is a defect in the hardware of the actual machine, it is possible to determine whether the operational defect discovered during debugging is due to the logic of the Zorogram itself, or whether it is due to incorrect wiring. It is difficult to determine whether the problem is caused by a hardware defect, such as the failure of a circuit element or a defect in the hardware described in Chapter 1, and elucidating the cause is often extremely difficult. There is.

The present invention has an extremely simple configuration that enables debugging of a program including input/output operations in a desired system independently of the actual hardware.
This is intended to shorten the development period.

The present invention will be described in detail below based on examples.

Reference numeral 1 indicates an input/output boat simulator of the present invention, and the simulator 1 is used in series with the CPU signal line of the microcomputer development apparatus. Such a connection method may be determined as appropriate depending on the configuration of the development apparatus 2, as long as the CPU signal line is connected.

For example, as shown in Figure 2, a CPU socket 4 is provided on the panel 3 of the simulator of the present invention, and a plug (not shown) of the in-circuit emulator of the development device 2 is inserted and connected to this socket. This has the advantage that connection is easy and the functions of an in-circuit emulator can also be used. Stain remover 1 of the present invention
In addition to being configured separately from the development device 2 as in the first embodiment described above, it may also be configured to be integrated into the development device 2.

However, the simulator 1 of the present invention uses the CPU of the development device 2.
Address display section 6 and data display section 7 connected to signal line
It also includes an input/output display section 8, a data input section 9, and a control signal generation section 10 for placing the CPU 5 of the development apparatus 2 in a waiting state. At least the input/output display section 8, the data input section 9, and the control signal generation section 10 are configured to operate for each input/output boat access signal of the CPU 5, and the control signal generation section 10 is 1 Kuwasaku switch 1 to release the wait state
1 will be provided. The address display section 6 and the data display section 7 may be configured to be operated for each input/output boat access signal, similarly to the input/output display section 8, data input section 9, and control signal generation section 10. , as shown in the figure, may be in a constant operating state regardless of the presence or absence of the output port access signal.

The specific circuits, elements, etc. of the following configuration may be designed as appropriate. In FIG. 2 showing an actual flow mode of the present invention, reference numeral 12
is an address bus, and 13 is a data bus.

14 is a write signal line, 15 is a consecutive output signal line, 1G is an input/output boat access signal line, and 17 is a wait signal line. Also, 18 is an address differential, and 19 is a 7 segment. This is a display section such as a display element.

In this configuration, when modifying a newly created program, the operator connects the simulator 1 of the present invention to the CPU signal 'tNs of the development device 2 as described above, and then CT-)Ub is operated based on the program to be debugged. However, C
When the instruction to be executed by the PU 5 is an input/output instruction for the input/output boat, the CPU 5 separates the CPU signal signal line and issues an input/output access signal to the simulator 1, and immediately sends the input/output access signal to the simulator 1. The wait state is maintained by the wait signal from the control signal generator (4) 10 which is activated by the control signal generator (4). This waiting state is canceled by the operation switch 11, and the CPU 5 thus proceeds with the instruction execution.

When the present invention is used, the CPU 5 goes into a waiting state immediately after issuing the input/output access signal and the progress of instruction execution is temporarily stopped, and this state is maintained unless the operation switch 11 is operated. During this time, the operator can read the address of the accessed input/output boat using the address display section 6, and can read whether the command is an input command or an output command using the input/output display section 8. Therefore, if the instruction is an output instruction, the output data can be read by the data display section 7, and the output instruction can be debugged by comparing it with a list or the like to see if the output data is equal to a predetermined value. can. If the command is an input command, the operator sets predetermined input data in the data manual section 9, such as a toll switch, and then operates the operation switch 11 to control the CPU.
CP[J 5
A predetermined input command can be executed. As described above, the present invention is capable of simulating input/output commands for all input/output hosts, and while continuously performing such operations, By operating the CPU S and analyzing malfunctions that occur during operation, the program can be debugged, that is, defects can be removed. This debugging work is performed completely independently of the actual machine that may have hardware defects, so it is completely unaffected by the actual machine's hardware defects.
Therefore, the causes of malfunctions are all due to the logic of the logic, which is easy to analyze, and can greatly contribute to shortening the development period of microcomputer application systems.

Furthermore, when debugging input/output commands as described above,
For example, if a specific input/output port is accessed at each execution of multiple locations in a program, it is possible to determine which location in the program the input/output command for the currently accessed input port was executed. There are times when it is convenient, and times when it is essential to understand. As a method for knowing the location of such a program, there is a method such as setting a break point at an appropriate location in the program using the development device 2, but in the present invention, the address display section 6 has the configuration of the embodiment shown below. This allows you to easily know the parts of the program written in IiJ. That is, in this embodiment, the address display section 6 is provided with an address storage section 20,
The address storage section 20 can display, in addition to the currently accessed input/output address, the most recently accessed address, even if it is alive. The address storage unit 20 stores the memory address and input/output address appearing on the address bus 12, for example, for each memory access signal or each memory access signal and input/output access signal. A plurality of addresses are sequentially memorized while pushing out the first-in address that was accessed several times before from the address, and when the address thus stored is input/outputted, an appropriate operation switch (not shown) is pressed as necessary. FIFO that is first in, first out by operating etc.
) method or first-in-last-out method (FILO) method, and as described above, the memory address accessed immediately before the input/output address P is displayed. The address that can be displayed may be only the memory address immediately before the current input/output port address, or may be a plurality of addresses before that. The display method may be, for example, as shown in FIG. 6 (IIL), in which the display section 19 for displaying input/output host addresses is shared and the display address is changed over with an appropriate switch 21, or a third
As shown in Figure (b), a dedicated display section 19' may be provided so that the immediately preceding address can be displayed at all times.

However, when the above embodiment is applied, even when a specific input/output port or multiple input/output ports are accessed at multiple locations in the program each time the program is executed, the address of the currently accessed input/output port is In addition, you can at least know the previous memory address, so
It is easy to see which part of the program the input/output command for the currently accessed input/output port was executed, and therefore it is easy to understand even if the input/output data of each input/output port differs depending on the access factor. Moreover, it is possible to reliably emulate input/output commands for each, and thus the present invention can be applied to the C'PU on which the program is to be developed.
Since it is possible to execute simulated input/output for all the input/outputs targeted by the software, debugging of Zorojiram can be carried out completely independently of the actual device, that is, it is possible to perform the debugging work of Zorojiram completely independently of the actual device. It has the great feature of being able to perform efficiently without being influenced at all. Moreover, the present invention has an extremely simple structure, is less likely to fail, and can be constructed at low cost.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of an example of the overall configuration, Figure 2 is an explanatory diagram of the external appearance,
FIGS. 6(a) and 6(1)) are explanatory diagrams of the other side of the main part configuration. Code 1: simulator, 2: development device, 3: panel, 4: socket, 5: CPU1ti: address display section, 7: data display section, 8: input/output display section, 9...Data input section, 10...Control signal generation section,
11・Operation switch, 12・Address bus, 13...
Data bus, 14...Write signal line, 15 - Successive signal line, I6...I/O boat access signal line, 17...Waiting signal line, 1st...Address decoding section, 19.19
'... Light display section, 20...-address storage section, 21 switch, 22... Memory access signal line, S = C
PU signal line. Applicant Ken Kinoshita Makoto Nikishita - Agent Koji Sanei (11) Figure 1

Claims (2)

[Claims] (1) An address, data, and input/output display unit and a data input unit connected to the CPU signal line of the microcomputer development device, and a configuration in which the CPU is operated in a waiting state and each input/output boat access signal of the CPU. and an input/output boat simulator for a microcomputer development device, characterized in that the control signal generating section is provided with an operation switch for canceling the wait state of the CPU. (2) An address storage section is provided in the address display section,
The microcomputer development apparatus according to claim 1, wherein the address storage unit is capable of displaying at least the address accessed immediately before, in addition to the input/output address currently accessed. input/output boat 7 simulator