JPS61201344A - Microcomputer - Google Patents

Abstract

PURPOSE:To test the function of an instruction sequence in a ROM by a customer's program by providing a means for ignoring a branch instruction, a skip instruction, and a data setting instruction to a memory which are read out of the ROM. CONSTITUTION:The customer's program stored in the ROM 1 is sent out to an instruction decoder 5 successively from the address '0' and a microcomputer operates. In this case, when the branch instruction is sent out of the ROM 1 to the decoder 5, a branch instruction inhibiting signal S5 is outputted and this instruction is ignored by an AND gate 9. Further, when the skip instruction is sent from the ROM 1 to the decoder 5, a skip instruction inhibiting signal S7 is outputted and a judging signal S3 is ignored. Therefore, even when the customer's program has a loop, the loop is ignored and instructions of the program stored in the ROM 1 are executed from the address '0' to the final address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer equipped with a ROM in which a customer's program is stored.

[Conventional technology]

Conventionally, testing of this type of microcomputer involves a functional test in which the microcomputer is switched to a test state, commands are input from the outside through the input terminals of the microcomputer during the test state, and the response is compared with expected values, and a function test is performed to test the customer's program. The test consists of a ROM content confirmation test in which information on each address of the ROM in which is stored is output from a computer terminal and compared with expected value information created in advance based on the customer's program.

[Problem that the invention seeks to solve]

The commands input in a functional test are created by the manufacturer of the microcomputer, so the sequence of commands is limited, whereas there are an infinite number of command sequences based on customer programs stored in the ROM. '
In the ROM content confirmation test, the customer's commands were correctly written to the ROM.
It only checks whether the customer's program is stored in the OM, but cannot confirm whether the customer's program correctly operates the microcomputer.

For this reason, conventional microcomputers may pass tests conducted by the manufacturer, but may not operate correctly when they are mounted due to defects caused by the combination of instructions.

An object of the present invention is to provide a microcomputer that can check whether a customer's program stored in a ROM operates the computer correctly.

[Means for solving problems]

The present invention is characterized by comprising means for ignoring branch instructions, skip instructions, register and/or memory data setting instructions when they are read from the ROM during a ROM content confirmation test. .

Therefore, if there is a loop in the customer's program, the loop is ignored, and the next instruction after the skip instruction that is not executed due to the conditions of the program can also be executed. Since the execution is executed up to the address, and data setting to registers and memory is prohibited during the test, the data of the calculation result is not destroyed, and the execution result can be compared with the expected value created in advance. The functions of the microcomputer can be checked for each instruction sequence according to the customer's program.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a microcomputer according to the present invention.

A customer's program is stored in the ROMI. The address decoder 3 decodes the count value of the program counter 2 to generate a ROMI address. The instruction decoder 5 connects the ROMI through the data bus 4.
It decodes the instruction read out from the memory and outputs a load signal S1 in the case of a branch instruction, a data setting signal S2 in the case of a register or memory data setting instruction, and outputs a data setting signal S2 in the case of a skip instruction, to the next address of the skip instruction. A judgment signal S3 indicating whether or not to execute a certain command is input. When the instruction read from the ROMI is a register or memory data setting instruction, a data setting signal S2 is output from the instruction decoder 5 to the memory 6 or register 7, and the data set by the instruction is normally stored. The prohibition signal generation circuit 8 is a ROMI during microcomputer testing.
In the case of a function confirmation test using a program built in, the test status signal S4 is enabled, and the branch instruction prohibition signal S5, data setting instruction prohibition signal S6, and skip-2 skip instruction prohibition signal S5, all of which are at low level, are activated. occurs. At this time, the program counter 2 is reset by the reset signal S7. The AND gate 9 normally passes the load signal SL from the instruction decoder 5 to load the address data from the ROM 1 into the program counter 2, but when the branch instruction prohibition signal S5 is output, it closes and ignores the load signal S1. . The AND gate 11 normally passes the data setting command 32 from the instruction decoder 5 and stores the data in the memory 6 or register 7, but when the data setting command prohibition signal S6 is output, it closes and ignores the data setting signal S2. do. The AND gate 10 normally sends the judgment signal S3 to the instruction decoder 5, but when the skip instruction prohibition signal S7 is output, it closes and ignores the judgment signal S3.

Next, the operation of this embodiment will be explained.

During a function confirmation test using a program built in the ROM 1 during a microcomputer test, the test status signal S4 causes the prohibition signal generation circuit 8 to generate a branch instruction prohibition signal S5. The data setting command inhibit signal S6 and the skip command inhibit signal S7 are generated, and the reset signal Sf sets the program counter 2 to address O.0 Next, the program counter 2 is incremented in order from address O of the ROMI. Each instruction is sent to the instruction decoder 5. The instruction decoder 5 decodes instructions and sends signals to various parts of the system to operate the microcomputer.

Branch instruction is sent from ROMI to instruction decoder 5
, the load signal Sl is generated, but since the 1 branch instruction prohibition signal S5 is output, the AND gate 9
will be ignored. Furthermore, when a skip command is sent from the ROMI to the instruction decoder 5, the judgment signal S3 is ignored because the skip command prohibition signal S is output. Therefore, a loop occurs in the customer's program. Even if there is a loop, the loop is ignored, and the next instruction after the skip instruction that is not executed due to program conditions can also be executed, so that the program instructions stored in the ROMI are executed sequentially from address 0 to the last address.

Furthermore, when a register/memory data setting command is sent from the ROM 1 to the instruction decoder 5, a data setting signal S2 is generated, but a data setting command prohibition signal S
6 has been generated, it is ignored by the AND gate 11. Therefore, it is not possible to change the data in register 7 and memory 6 due to a loop in the customer's program, but by prohibiting register and memory data setting instructions, there are several ways to change the data at the time of initialization during the function confirmation test. data can be set in the memory 6 and register 7.

The expected value of each terminal of the microcomputer during the test is created in advance based on the customer's program, and by executing the program in the ROMI and comparing it with the expected value, the commands from the customer's program can be determined. The functions of the microcomputer can be checked for each sequence.

However, in this case, the combination of the branch instruction and the instruction at the destination address of the branch instruction may not be confirmed, but in the functional test described in [Prior Art], in the combination test of the branch instruction and other instructions, By testing combinations of branch instructions and other instructions, all instruction sequences in the customer's program have been confirmed.

〔Effect of the invention〕

As explained above, the present invention provides means for ignoring branch instructions, skip instructions, register and/or data setting instructions read from the ROM when these instructions are read during a ROM content confirmation test. This feature has the great effect of reducing defects caused by combinations of instructions during functional tests of ROM instruction sequences based on customer programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of a microcomputer according to the present invention. 1: ROM, 2 Niprogram counter, 3: Address decoder f, 4: Data nox, 5: Instruction decoder. 6: Memory, 7: Register. 8: Prohibition signal generation circuit. 9, to, 11: and gate. SL: Load signal, S2: Data setting signal. S3: Judgment signal, S4: Test status signal. S5: Branch instruction prohibition signal. S6: Data setting command prohibition signal, S7: Skip command prohibition signal, S7: Reset signal.

Claims (1)

[Scope of Claims] In a microcomputer equipped with a ROM in which a customer's program is stored, during a content confirmation test of the ROM, a branch instruction, a skip instruction, and an instruction to set data to a register and/or memory are read from the ROM. A microcomputer characterized in that the microcomputer is equipped with means for ignoring these instructions when the instructions are issued.