JPS62145437A - Computer - Google Patents

Abstract

PURPOSE:To execute a program stored in a read only memory by providing a means inhibiting a skip instruction and executing an instruction stored in the read only memory at test. CONSTITUTION:A branch instruction and skip instruction inhibition signal generating circuit 8 is operated by a test state signal 9 and a program counter 7 is set to address '0' by a program counter reset signal 5. When a skip instruction is sent from a ROM 1 to an instruction decoder 3, a judging signal 12 whether or not the instruction of the next address of the skip instruction is executed is sent to the decoder 3 normally and since the circuit 8 is in operating state, a skip instruction inhibition signal 11 is generated and the signal 12 is disregarded. Thus, the instruction next to the skip instruction not executed by the program condition is executed and the sequence of the instruction by the program stored in the ROM 1 is executed sequentially from the address '0' to the final address.

Description

[Detailed Description of the Invention] [Technical Field] It is equipped with a read-only memory (hereinafter referred to as ROM) that stores a customer's program, and stores it in read-only memory while prohibiting branch instructions and skip instructions during testing. Relating to a computer that can run programs.

[Prior art]

A micro combinator with a built-in ROM is used as an example.

Microcombiator testing involves switching the microcomputer to a test state, inputting commands from the outside through the microcombiator's input terminals during the test state, and comparing the response with the expected value.The test also involves a functional test in which the customer's program is stored. A ROM contents confirmation test is performed by outputting information on each address of the ROM from the combination terminal and comparing it with expected value information created in advance based on customer i's program.

The commands input during the functional test are created by the manufacturer that installs the micro combinator, so the sequence of commands is limited.

In contrast, there are an infinite number of customer program instruction sequences stored in ROM. R in the ROM content confirmation test
The OM only checks whether the customer's instructions are correctly stored in the ROM, but cannot check whether the customer's program correctly operates the microcombi machine.

For this reason, although the product was found to be good in tests conducted by the manufacturer, it sometimes did not work properly when it was installed due to defects caused by the combination of instructions.

[Purpose of the invention]

The present invention has been developed in order to eliminate the above-mentioned drawbacks, and to check whether the customer's program stored in the ROMK is correct and can operate the comviator during testing, the customer's program is stored in a read-only ROMK. To provide a computer equipped with a memory and a simple circuit capable of executing a program stored in a read-only memory while prohibiting branch instructions and skip instructions during testing.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention.

Test status signal 9 during a function confirmation test using a program built into the ROM during a microcomputer test
The branch instruction and skip instruction prohibition signal generation circuit 8 is activated, and the program counter counter 7 is set to address θ by the program counter rehit signal 5.

The next program counter is incremented, and instructions are sequentially transmitted to the instruction decoder 3 starting from address θ. The instruction decoder 3 sends signals to various parts of the system to operate the micro combiator. When a branch instruction is sent from the ROM to the instruction decoder 3, a load signal 4 is generated to load the address data from the ROM 1 to the program counter 7, and the address data from the ROM is set in the program counter 7.
In this case, since the branch instruction and skip instruction prohibition signal generation circuit is in the operating state, the address load instruction 4 is ignored from the instructor 1 decoder because the branch instruction prohibition signal 6 is at a low level.

Additionally, when a skip instruction is sent from the ROM to an instruction decoder, a judgment signal 12 is normally sent to the instruction decoder to determine whether or not to execute the instruction at the address next to the skip instruction, but a branch instruction and skip instruction prohibition signal is generated. Since circuit 8 is in operation,
A skip command prohibition signal 11 is generated, 11 is set to low level, and the judgment signal 12 is ignored. For this reason, even if a loop is created in the customer's program, the loop can be ignored, and the instruction following the skip instruction that is not executed depending on the program conditions can also be executed. The sequence is executed sequentially from address 0 to the last address.

The expected value of each terminal of the micro combinator during this test is created based on the customer's program.In this way, by running the program in the ROM and comparing it with the expected value, the customer's The functions of the microcomputer can be checked for each instruction sequence by the program.

However, in this case, the combination of the branch instruction and the instruction at the destination address of the branch instruction may not be confirmed, but in the functional test described in the above-mentioned [Prior Art], the combination of the branch instruction and other instructions may not be confirmed. During testing, if a combination of branch instructions and other instructions is tested, all instruction sequences in the customer's program have been confirmed.

〔Effect of the invention〕

As explained above, it is possible to perform a functional test of the instruction resistance of a ROM according to a customer's program using a simple circuit, which has the great effect of reducing defects caused by combinations of instructions.

[Brief explanation of drawings]

The first factor is a diagram showing an embodiment of the present invention. 1...Read-only memory (ROM), 2...
...Data bus from ROM, 3...Instruction decoder, 4...Address load signal, 5...Reset signal, 6...
Branch instruction prohibition signal, 7...Program counter, 8...Branch instruction and skip instruction prohibition signal generation circuit, 9...Test mode signal, 10.
..., ROM address decoder, 11...
Skip command prohibition signal, 12...judgment signal.

Claims (1)

[Claims] 1. A computer comprising a built-in read-only memory, a means for prohibiting branch instructions and skip instructions during testing, and executing instructions stored in the read-only memory.