JPH01102646A - Processor control system - Google Patents

Abstract

PURPOSE:To easily carry out the check of faults for each function with the use of an oscilloscope by switching the logic levels of a terminal to carry out a routine instructed by a fault checking mode as necessary without stopping an operation. CONSTITUTION:A designating means 1 is set previously to designate the execu tion of a fault checking mode and therefore, a logic circuit 2 reads a mode instruction means 4 out of a ROM 3. The circuit 2 does not stop its working to carry out the fault checking mode instructed by the means 4. Thus, it is possible to check the situations of a processor and the peripheral circuits via an oscilloscope and to know the fault state within each function. As a result, both the cost and the time can be reduced for diagnoses.

Description

[Detailed Description of the Invention] [Summary] When exception processing such as execution of an undefined instruction or execution of an incorrect address occurs, and when exception processing occurs again while this processing is being executed,
In a processor that has a function to stop operation, even if an exception occurs again during execution of an exception, the cause of the failure can be easily investigated by continuing to execute the routine instructed by the failure investigation mode without stopping the operation. With regard to the processor control method that is used to control the processor, it is possible to grasp the operating status of the processor using an oscilloscope, and the purpose of this is to reduce diagnostic costs and time, and to instruct the processor to execute a fault investigation mode. and a designation means for instructing the mode designation means to execute the fault investigation mode, and the mode designation means instructs the processor to execute the fault investigation mode based on the designation of the designation means. When exception processing occurs again while the processor is executing exception processing, the processor is configured to operate at mVt and continue to execute the routine instructed by the fault investigation mode. [Field of Industrial Application] The present invention has a function to stop the operation when an exception processing such as execution of an undefined instruction or execution of an incorrect address occurs, and when an exception processing occurs again while this processing is being executed. Regarding the processor,
In particular, the present invention relates to a processor control method that facilitates investigation of the cause of a failure by continuing to execute a routine instructed by a failure investigation mode without stopping operation even if an exception occurs again during execution of an exception.

In recent years, there has been a strong demand for improved performance in information processing devices, and it has become difficult to control the entire device with a single processor. A single processor is provided in each unit to control each functional unit. A necessary number of these functional units are put together to form one information processing device.

By the way, when a processor that controls this functional unit is given an undefined instruction to the processor and is requested to execute this instruction, it executes exception handling to escape from this abnormal state. do. That is, for example, if an error processing address is sent to a ROM or the like and the error processing contents are read out, but if an exception occurs again, such as when the error processing contents are abnormal, some operations stop. .

This is expected to have a great effect in preventing a problem from spreading due to a runaway of the processor, etc., if a problem occurs during the operation of a functional unit.

However, it is necessary to be able to easily investigate faults in functional units.

[Conventional technology]

FIG. 4 is a flowchart illustrating the operation of a conventional processor.

When a functional unit is powered on, a reset signal is first input to the processor, and the processor reads initial setting values from a ROM or the like. Then, it is checked whether or not there is an error in the read initial setting value, and if there is no error, a reset signal within the functional unit is started.

That is, initial settings of LSi etc. incorporated in the functional unit are performed.

If there is an error in the read initial setting value, an address for error handling is sent to a ROM or the like, and content instructing error handling is read out. If there is no error in the read error processing contents, execution of the error processing is started, but if there is an error, the processor stops operating.

[Problem that the invention seeks to solve]

As described above, conventionally, if an exception occurs again during execution of an exception, the processor stops operating. In other words, the processor is uniquely stopped regardless of the situation, making it difficult to investigate faults in functional units.

In other words, the functional unit usually consists of a printed circuit board unit, and it is possible to test it alone, but since the processor stops in a short time (several μs), it is difficult to grasp the operating status with a simple oscilloscope. I can't do it.

For this reason, especially when testing printed board units at factories, addresses and data may be incorrect due to defects in parts such as LSI mounted on the printed board units, short circuits between wiring, etc., but these failures can be detected. To do this, it is necessary to equip a high-grade diagnostic device such as a logic analyzer, which raises the problem of increased diagnostic cost and time.

The present invention includes a mode instruction means for instructing a processor to execute a fault investigation mode, and a specification means for specifying whether or not the mode instruction means is to instruct the execution of the fault investigation mode. When the mode instruction means instructs the processor to execute the fault investigation mode based on the specification, when the processor is executing exception processing and an exception occurs again, the operation is continued and the fault investigation mode is switched off. The purpose of this system is to keep the instructed routines running, thereby making it possible to grasp the operating status of the processor using an oscilloscope, thereby reducing diagnostic costs and diagnostic time.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

The logic circuit 2 of the processor 5 starts operation by reading a program stored in the ROM 3, and reads initial setting values from the ROM 3 upon input of a reset signal as shown in FIG. Then, it is checked whether or not there is an error in the read initial setting value, and if there is no error, reset processing within the functional unit is started.

If there is an error in the read initial setting value, an address for error handling is sent to a ROM or the like, and content instructing error handling is read out. If there is no error in the read error processing contents, execution of the error processing is started, but if there is an error, the processor checks whether the specifying means 1 has specified execution of the fault investigation mode.

If the specifying means 1 does not specify the execution of the fault investigation mode, the logic circuit 2 stops operating, but if the specifying means 1 specifies the execution of the fault investigation mode, the mode instruction means 4 is read from the ROM 3, and the logic circuit 2 stops operating. The routine instructed by the mode instruction means 4 is executed.

[Effect]

By configuring as described above, if the specifying means 1 is set to specify execution of the fault investigation mode, the logic circuit 2 reads the mode specifying means 4 from the ROM 3, and detects the fault specified by the mode specifying means 4. To execute the investigation mode, the logic circuit 2 does not stop operating.

Therefore, by checking the status of the processor and its peripheral circuits using an oscilloscope, it is possible to know the failure status within the functional unit.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a flowchart illustrating the operation of FIG. 2.

The logic circuit 2 of the processor 5 reads the program stored in the ROM 3 and starts its operation, and as shown in FIG. The address is sent, and the initial setting value read from the ROM 12 is taken in via the data processing circuit 11.

Then, it is checked whether or not there is an error in the read initial setting value, and if there is no error, the address generation circuit 10 is controlled to create and send an address within the functional unit, for example, LSi, etc. A reset process is started in which the signal generation circuit 9 is controlled to send out a control signal and the initial setting values of these LSis are set.

Then, through the data processing circuit 11, data is sent and received to and from the cough LSi and the like.

The logic circuit 2 detects errors when there is an error in the read initial setting value, that is, when the code of the instruction read from the ROM 12 changes and becomes an undefined instruction, the instruction contents are unknown, or when the address is wrong. If the branch destination is incorrectly calculated, the error processing address corresponding to the error content is sent to the ROM 12, and the error processing content is read out.

Then, it is checked whether or not there is an error in the read error processing content, and if there is no error, the error processing specified by the error processing content is executed.

If there is an error in the read error processing content,
Logic circuit 2 checks whether execution of the fault investigation mode has been instructed. That is, the logic level of terminal 7 is checked via the input port.

For example, if terminal 7 is grounded and the logic level is "0", the execution of the fault investigation mode is not instructed, and if power +■ is applied to terminal 7 and the logic level is "1", the fault investigation mode is not instructed. When the logic circuit 2 is notified from the input port that the logic level of the terminal 7 is "1", it indicates that the fault investigation mode is to be executed, and from the ROM 3. Read the mode instruction program 8.

Then, the mode instruction program 80 starts executing the instructing routine. That is, the error processing content is read from the error processing address of the ROM 12, and it is checked whether or not there is an error in the read error processing content. If there is an error again, the logic level of the input port is checked and the fault investigation mode is executed. Knowing this, the routine for reading out the error processing contents from the error processing address of the ROM 12 is executed again at '4'.

Logic circuit 2 has a logic level of terminal 7 from the input port.
When it is notified that the status is "O", it recognizes that the failure investigation mode is not being executed and stops the operation.

〔Effect of the invention〕

As explained above, the present invention is a processor that has a function to stop operation when an exception occurs and another exception occurs while this process is being executed, by switching the logic level of the terminal. Since it is possible to execute the routine instructed by the fault investigation mode without stopping the processor, it is possible to easily investigate faults in functional units using an oscilloscope without stopping the processor.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 3 is a flowchart explaining the operation of FIG. 2, and FIG.
The figure is a flowchart explaining the operation of a conventional processor. In the figure, 1 is the designation means, 2 is the logic circuit, and 3.12 is the RO.
M, 4 is a mode instruction means, 5 is a processor,
6 is an input port, 7 is a terminal, 8 is a mode instruction program, 9 is a control signal generation circuit, 10 is an address generation circuit, Figure 1

Claims (1)

[Claims] When an exception process such as execution of an undefined instruction or execution of an incorrect address occurs, and another exception process occurs while this process is being executed,
In a processor (5) having a function to stop operation, a mode instruction means (4) for instructing the logic circuit (2) of the processor (5) to execute a fault investigation mode, and a mode instruction means (4) for instructing the logic circuit (2) of the processor (5) to A designating means (1) for instructing execution of the investigation mode is provided, and based on the designation of the designating means (1), the mode instructing means (
4) instructs the logic circuit (2) to execute the fault investigation mode, and when exception processing occurs again while the processor (5) is executing the exception processing, the operation of the processor (5) A processor control method characterized by continuing to execute a routine instructed by the failure investigation mode.