JPH01154248A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the test of a microcomputer by outputting the data contents of a built-in program ROM to an external terminal when an internal function action is confirmed based on the external instruction data. CONSTITUTION:When a test mode setting signal ST is set at '1', the '1' sides of input/output selection circuits 31 and 30 are actuated. Then the external instruction data D1 is selected through an external instruction data input terminal TI and read into an instruction register 6. At the same time, the program ROM data DPR is supplied to a program ROM output terminal TPR. In case the signal ST is set at '0', the data DPR is read into the register 6 from the '0' side output terminal of the output selection circuit 30 via the '0' side of the input selection circuit 31.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present inventors relate to logic integrated circuits, particularly read-only memories (
The present invention relates to a logic integrated circuit having a test circuit for a single-chip microcomputer incorporating a built-in ROM (hereinafter referred to as ROM).

[Conventional technology]

With the recent increase in the scale of microcomputers, it has become necessary to shorten their self-test time.

In general, a single-chip microcomputer that has an internal program ROM and executes operations based on the instructions and data in the ROM can perform the following two self-tests to enable functional tests inside the logic integrated circuit. has a mode.

(1) In instruction insertion mode, external instruction data is fetched and executed via the general-purpose input/output terminal to check the function operation of the internal circuit.

(2) ROM dump mode, the built-in program R is transferred via the general-purpose input/output terminal.
By outputting the contents of OM, programno, RO
Check M's memory data.

FIG. 3 is a block diagram of an example of a conventional logic integrated circuit.

The microcomputer 1b includes an output selection circuit 3o that inputs the program ROM/data DPR output from the program ROM 5, and a ROM/data output from the "O" side of the output selection circuit 3o.
Data DPR and external instruction data D+
an input selection circuit 31 which inputs and supplies it to one of the instruction registers 6, an inverter 9 and a NAND circuit 10 having an instruction insertion mode setting terminal TTF and a ROM dump mode setting terminal TTR as inputs.
via an input control terminal TI and an output control terminal T.

The test mode setting unit 4b has a test mode setting unit 4b as an output, and an ALU 2 and a RAM II connected to the data bus DB.

Next, the circuit operation when each test mode is set will be explained.

When setting the first instruction insertion mode, the instruction insertion mode signal STF at the level "1°" is applied to the instruction insertion mode setting terminal TTF, and
When the OM dump mode setting signal STR is at "0 level", only the input control terminal TI becomes "1" level due to the logic operation of the internal inverter 9 and NAND circuit 10, and the external instruction/data DI passes through the input selection circuit 3I. and is read into instruction register 6.

When setting the second ROM dump mode, when the ROM dump mode setting signal STR at the "1'° level is applied to the ROM dump mode setting terminal TTR, the signal STR is supplied to the input control terminal T. from one output terminal of the program ROM to the program ROM output terminal TPR.
Data DPR outputs.

In this circuit, when the instruction register of external instruction data D+ is read, the program ROM data DPR of the program ROM 9 is unselected by the interpretation circuit 3o due to the operation of the input/output selection circuit based on the logic operation of the test mode setting section. Program output terminal TPR
is not output to .

In addition, in ROM dump mode, the built-in program ROM
9, the operation of the instruction decoder 7 was prohibited.

[Problem that the invention seeks to solve]

The conventional logic integrated circuit described above has an instruction insertion mode in which a function operation confirmation test is performed using external instruction data in a function self-test mode, and a built-in program ROM.
Since the ROM dump mode and the ROM dump mode for checking data are independent modes, when checking the operation by external instructions, the program ROM data output is usually separated from the instruction register, and if the ROM dump mode is Even if the program counter that determines the address malfunctions midway through, it is difficult to confirm, and even if there is a way to confirm, it can be confirmed by outputting the address value saved in memory by a subroutine call instruction, etc. to a general-purpose output terminal. There was a problem in that a complicated method had to be used.

An object of the present invention is to provide a logic integrated circuit having a test circuit that is in ROM dump mode at the same time as external instruction insertion mode.

[Means for solving problems]

The logic integrated circuit of the present invention includes an output selection circuit that inputs output data of a program ROM and selects and outputs it to one of two output terminals, and output data of one of the output selection circuits and external instruction data to two output terminals. an input selection circuit whose output terminal selects one of the two data and supplies it to the instruction register; and an input selection circuit which inputs a test mode setting signal to at least one test mode setting terminal and selects the input and output. and a test mode setting section that supplies the test mode setting signal to the input and output control terminals corresponding to the circuit, and operates according to the instruction data of the program ROM in the normal operation mode, and operates in the test mode in the self test mode operation. In the logic integrated circuit that operates according to the external instruction data according to the setting signal, the test mode setting signal is supplied to the input and output control terminals, and the program ROM data is outputted to the outside via the output selection circuit. The external instruction data is input to the instruction via the input selection circuit.
It is configured by inputting it into a register.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The microcomputer 1 is the same as the conventional microcomputer 1b except that the test mode setting section 4 is different from the test mode setting section 4b shown in FIG.

The test mode setting section 4 has a test mode setting terminal TT, input and output control terminals TI and To, and a wiring 11 that commonly connects them.

Next, the operation will be explained.

When the test mode setting signal ST is at the "1" level, the "1" side of the input and output selection circuits 3I and 3o operates, and the external instruction data D+ is selected from the external instruction data input terminal TI, and the instruction register At the same time as the program R
OM data DPR is supplied to program ROM output TPR.

On the other hand, when this test mode setting signal S is at "0" level, the program ROM data [)pyt is transferred from the "0" side output terminal of the cutting edge circuit 3o to the input selection circuit 31.
It is read into the instruction register 6 via the 0'' side.

Therefore, the microcombi eater 1 is in a normal use mode in which the instruction decoder 7 operates based on the data signal of the instruction register 6.

Here, when the microcomputer 1 is in the self-test mode, the external instruction data is D! While performing a function operation confirmation test, the program ROM data DPR of the program ROM 5 corresponding to the address of the program counter 8 is output to the TPR at the program ROM data end, albeit indirectly. It also becomes possible to test the operation of the program counter 8.

FIG. 2 is a block diagram of a second embodiment of the invention.

The microcomputer 1a includes a test mode setting section 4.
is the same as the microcomputer 1 of the first embodiment except that it is different from the test mode setting section 4 of FIG.

Test mode setting section 4. has two input terminals, an instruction insertion mode setting terminal TTF and a ROM dump test mode setting terminal TTR, and the corresponding input control terminal T+.
and output control terminal T. are connected by wires e2 and e3.

By setting the two j-code setting terminals TTF and TTR to the "1" level at the same time, the external instruction data D1
It is also possible to indirectly check the operation of the internal program counter 8 by outputting the internal program ROM data DPR to the program ROM output terminal TPH while executing the test.

〔Effect of the invention〕

As explained above, in the self-test mode of the logic integrated circuit, the present invention constantly outputs the data contents of the built-in program ROM to the external terminal when testing the internal function operation using external instruction data. - The operation of the counter can be checked indirectly, making it easier to test microcomputers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of an example of a conventional logic integrated circuit. 1.1a...Microcomputer, 3I...Input selection circuit, 3o...Output selection circuit, 4 and 41...
Test mode setting section, 5... program ROM, 6.
...Instruction register, D+...External instruction data, DPR...Program R
OM/data, 8 pieces...Test mode setting signal, T1
...Input control end, To...Output control end, TI...
External instruction/data input terminal, TPR...
Program ROM output terminal, TT... test mode setting terminal, TTF... instruction insertion mode setting terminal, TTR... ROM dump mode setting terminal.

Claims (1)

[Claims] An output selection circuit that inputs output data of a program ROM and selectively outputs it to one of two output terminals, and an output terminal that inputs output data of one of the output selection circuits and external instruction data to two input terminals and outputs it selectively to one of two output terminals. an input selection circuit that selects one of the two data and supplies it to the instruction register; and an input and output that inputs a test mode setting signal to at least one test mode setting terminal and corresponds to the input and output selection circuit. and a test mode setting section that supplies the test mode setting signal to the control end, and operates according to the instruction data of the program ROM in the normal operation mode, and operates according to the external instruction data according to the test mode setting signal during the self test mode operation. In a logic integrated circuit operated by data, the test mode setting signal is supplied to the input and output control terminals, and the program ROM data is outputted to the outside via the output selection circuit, and the program ROM data is outputted to the outside via the input selection circuit. The external instructions
A logic integrated circuit characterized by inputting data to an instruction register.