JPH077343B2 - Micro computer - Google Patents

Description

The present invention relates to a microcomputer provided with a ROM that stores a customer's program.

[Conventional technology]

Conventionally, this type of microcomputer test is performed by switching the microcomputer to a test state, inputting a command from the outside through an input terminal in the test state of the microcomputer, and comparing the response with an expected value, and a customer program. This is a ROM content confirmation test in which the information of each address of the ROM in which is stored is output from the terminal of the computer and is compared with the expected value information created based on the customer's program in advance.

[Problems to be solved by the invention]

Since the command input in the functional test is created by the manufacturer of the microcomputer, the command sequence is limited, while the command sequence stored by the customer in the ROM is innumerable. ROM
In the content confirmation test, the ROM only confirms whether the customer's instructions are correctly stored in the ROM, and cannot confirm whether the customer's program operates the microcomputer correctly.

For this reason, although the conventional microcomputer is a non-defective product in the test performed by the manufacturer, it may not operate properly in the mounted state due to a defect resulting from a combination of instructions.

An object of the present invention is to provide a microcomputer capable of confirming whether a customer program stored in a ROM operates a computer properly.

[Means for solving problems]

The present invention, during the function confirmation test of the microcomputer,
When a branch instruction, a skip instruction, a data setting instruction to a register and / or a memory are read from the ROM, a means for ignoring these instructions is provided.

So when a customer program has a loop,
The loop is ignored, and the next instruction after the skip instruction that is not executed due to the condition of the program can also be executed. As a result, the instructions by the program stored in ROM are executed sequentially from address 0 to the last address, and the instruction sequence by the customer program is executed. The function of the microcomputer can be confirmed every time.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a microcomputer according to the present invention.

ROM1 stores the customer's program. The address decoder 3 decodes the count value of the program counter 2 to generate the address of the ROM 1. The instruction decoder 5 decodes the instruction read from the ROM 1 through the data bus 4, and in the case of a branch instruction, the load signal S
₁ , output the data setting signal S ₂ in the case of a register / memory data setting instruction, and input the judgment signal S ₃ in the case of the skip instruction whether the instruction at the address next to the skip instruction is executed or not To do. When the instruction read from the ROM 1 is a register or a memory data setting instruction, the memory 6 or the register 7 outputs the data setting signal S ₂ from the instruction decoder 5 and normally stores the data set by the instruction. . In the prohibition signal generation circuit 8, the test state signal S ₄ is enabled in the case of the function confirmation test by the program contained in the ROM 1 at the time of the microcomputer test, and the low level branch instruction prohibition signal S ₅ and the data Generates a setting instruction prohibition signal S ₆ and a skip instruction prohibition signal S ₇ . At this time, the program signal 2 is reset by the reset signal S ₇ . The AND gate 9 is a load signal from the normal instruction decoder 5.
The address data from ROM ₁ is loaded into program counter 2 through S ₁ , but when branch instruction disable signal S ₅ is output, it is closed and load signal S ₁ is ignored. And gate 11
Normally causes the data setting command S ₂ from the instruction decoder 5 to pass and stores the data in the memory 6 or the register 7, but when the data setting command prohibit signal S ₆ is output, it is closed and the data setting signal S ₂ is ignored. To do. The AND gate 10 normally sends the decision signal S ₃ to the instruction decoder 5, but closes when the skip instruction inhibition signal S ₇ is output and ignores the decision signal S ₃ .

Next, the operation of this embodiment will be described.

The test state signal S ₄ in function confirmation test by a program embedded in the ROM1 upon the microcomputer tests the branch instruction disable signal S ₅ from the inhibit signal generating circuit 8, the data setting command rejection signal S _6, the skip instruction disable signal S _{When 7} is generated and the reset signal S ₇ , the program counter 2 is set to the address 0. Next, the program counter 2 is incremented and instructions are sequentially sent to the instruction decoder 5 from address 0 of ROM1. The instruction decoder 5 decodes the instructions and sends signals to various parts of the system to operate the microcomputer.

When the branch instruction is sent from the ROM 1 to the instruction decoder 5, the load signal S ₁ is generated, but since the branch instruction prohibition signal S ₅ is output, it is ignored by the AND gate 9. Further, when the skip instruction is sent from the ROM 1 to the instruction decoder 5, the decision signal S ₃ is ignored because the skip instruction prohibition signal S ₇ is output. Therefore, even if the customer's program has a loop, the loop is ignored, and the instruction following the skip instruction that is not executed due to the condition of the program can also be executed. As a result, the instruction by the program stored in ROM1 starts from address 0 and ends at the end. It is executed up to the address.

Further, when the register / memory data setting instruction is sent from the ROM 1 to the instruction decoder 5, the data setting signal S ₂ is generated, but since the data setting instruction prohibiting signal S ₆ is generated, it is ignored by the AND gate 11. . For this reason, the data in the register 7 and the memory 6 cannot be changed by the loop of the customer's program, but by prohibiting the register and memory data setting instructions, there are several ways at the time of initialization during the function confirmation test. Can be set in the memory 6 and the register 7.

The expected value of each terminal of the microcomputer at the time of test is created in advance based on the customer's program, and by executing the program in ROM1 and comparing it with the expected value, the instruction by the customer's program The function of the microcomputer can be confirmed for each sequence.

However, in this case, the combination of the branch instruction and the instruction at the destination address of the branch instruction may not be confirmed, but in the functional test described in [Prior Art], in the combination test of the branch instruction and other instructions, By conducting a combination test of the branch instruction and another instruction, all the instruction sequences by the customer's program can be confirmed.

〔The invention's effect〕

As described above, the present invention provides means for ignoring a branch instruction, a skip instruction, a register and / or memory data setting instruction read from a ROM during a ROM content confirmation test. With the provision, the function test of the instruction sequence of the ROM can be performed by the program of the customer, and there is a great effect that the defects caused by the combination of the instructions are reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of a microcomputer according to the present invention. 1: ROM, 2: Program counter, 3: Address decoder,
4: Data bus, 5: Instruction decoder, 6: Memory, 7: Register, 8: Inhibit signal generation circuit, 9, 10, 11: AND gate, S ₁ : Load signal, S ₂ : Data setting signal, S ₃ : Judgment signal, S ₄ : Test status signal, S ₅ : Branch instruction disable signal,
S ₆ : Data setting instruction prohibition signal, S ₇ : Skip instruction prohibition signal, S ₇ : Reset signal.

Claims (1)

[Claims] 1. A microcomputer provided with a ROM in which a customer's program is stored, which is an instruction decoder for decoding an instruction read from the ROM, which is for a branch destination instruction when the branch instruction is decoded. An instruction decoder for generating a load signal to load address information into the program counter and receiving a judgment signal indicating whether or not to execute the instruction next to the skip instruction when the skip instruction is decoded, and a function confirmation test of the microcomputer. An inhibit signal generation circuit that generates a branch inhibit signal and a skip inhibit signal in response to a signal that is sometimes active, and a gate that masks the load signal and the decision signal in response to the branch inhibit signal and the skip inhibit signal, respectively. And having means Microcomputer that.