JPS6226738B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory protection circuit that protects a memory so that the contents of the memory circuit are not destroyed when a microcomputer malfunctions or goes out of control.

A conceptual diagram of the main parts of a conventional microcomputer system is shown in FIG. In this figure, 1 is a CPU (central processing unit), address bus 2, data bus 3, memory read signal (hereinafter referred to as MEMR signal) 4, memory write signal (hereinafter referred to as MEMW signal) 5, input/output A read/write memory 8 (hereinafter referred to as RAM memory) that outputs signals such as a read signal (hereinafter referred to as I/QR signal) 6 and an input/output write signal (hereinafter referred to as I/QW signal) 7, etc. and are connected as shown in the figure. 9 is a chip select signal (hereinafter referred to as CS signal) for the RAM memory 8;
This is a signal that decodes (not shown) the upper bits of the address bus 2 and selects them when a plurality of ICs are present. To read the RAM memory 8, select the corresponding memory address using the address bus 2 and the CS signal 9, and output the MEMR signal 4, and the data at the corresponding memory address will be transferred to the data bus 3.
will be output. This is done by reading this into the CPU1. Writing to RAM memory 8 is
The corresponding memory address is selected using address bus 2 and CS signal 9, and data bus 3 is selected from CPU 1.
When data is output to the MEMW signal 5 and the MEMW signal 5 is output, the data on the data bus 3 is written to the memory at the corresponding memory address.

However, in the above-mentioned conventional configuration, when the CPU 1 causes an abnormal operation, that is, a runaway operation, the memory write operation writes data to an unintended address.
Unintended data is written without permission and the memory contents are destroyed.

If such a runaway occurs in a microcomputer system that writes constants for calculations and control into the RAM memory 8 and performs calculation control based on these, it will not be possible to restart the operation unless the constants are written again at the time of recovery, so the recovery procedure was extremely complicated. Furthermore, if the system is large-scale, the number of constant points often reaches several hundred points or more.
The time required for resetting was often quite long.

The present invention has been made in view of these drawbacks, and it is an object of the present invention to provide a memory protection circuit configured so that data in a RAM memory in which constants are written will not be destroyed even if the CPU goes out of control. This invention will be explained below.

FIG. 2 shows one embodiment of the present invention, and is a schematic circuit diagram of an Intel 8085A series microcomputer system. In this figure, 1
0 is a RAM memory for setting and storing constants.
This includes the CPU (not shown) and address bus 1.
1, a data bus 12, and a MEMR signal 13, and a MEMW signal 14 is connected via a gate circuit 15. This gate circuit 15 is connected to the output (Q) of the D flip-flop 16, and the D terminal of the D flip-flop 16 is connected to the operation/setting switch 1.
7 and an inverter circuit 18. The operation/setting switch 17 is set to setting mode when ON, and OFF.
It is in operation mode when . Further, the T terminal of the D flip-flop 16 is connected to the address latch enable signal (hereinafter referred to as ALE signal) 19 of the CPU 1.
connected to.

When setting constants, the operation/setting switch 17 is set to the setting mode, that is, turned ON. Then, the D terminal of the D flip-flop 16 becomes "H" level, so when the T terminal is triggered by the ALE signal 19, its output Q becomes "H" level, and the gate circuit 15 becomes open. Here, the memory address for storing the constant is output to the address bus 11, and the data of the stored N constants is output to the data bus 11.
2 and outputs the MEMW signal 14, this output signal passes through the gate circuit 15 and reaches the RAM memory 10, where the data is written to the corresponding address. Since the ALE signal 19 is a signal at the beginning of the instruction machine cycle, the above-described operation procedure can be performed smoothly.

In this case, the state of the run/setting switch 17 is latched by the ALE signal 19, which is the first signal of the command, and the gate circuit 15 is thereby opened.
If you switch, the switch operation at the time of switching will not be valid, but will start from the switched state.
ALE signal 19 indicates the state of flip-flop 1.
It is latched at 6, and the switched state becomes valid from then on. Therefore, a half-finished memory write signal is never output.

When the setting operation is not performed, the operation/setting switch 17 is set to the operation mode, that is, OFF. Then, the D terminal of the D flip-flop 16 becomes "L" level, so when the T terminal is triggered by the ALE signal 19, its output Q becomes "L" level, and the gate circuit 15 is closed. Therefore, the MEMW signal 14 is blocked by the gate circuit 15 and does not reach the RAM memory 10. Therefore, data cannot be written. however,
Since the MEMR signal 13 is not provided with such a circuit, it can be read freely regardless of the mode of the operation/setting switch 17.

Here, if the CPU goes out of control during the operation mode, the MEMW signal 14 is blocked by the gate circuit 15 as described above, so that it is sent to an unintended address.
Unintended data will not be written to the memory contents.

Of course, if the CPU goes out of control while in the setting mode, the MEMW signal 14 will pass through the gate circuit 15, so in this case the memory contents may be destroyed, but normally the constant settings should be changed frequently. is small and therefore during configuration
The probability that the CPU will run out of control is extremely low. Therefore, the probability that memory contents will be destroyed due to runaway is:
This is significantly less than before.

Note that the present invention can be similarly carried out with other microcomputer systems such as the Intel 8085 series, Motorola 6800 series, and RCACD1800 series.

As described above in detail, the present invention includes a settable signal generating means, a gate circuit that opens upon application of the settable signal and allows a memo write signal to pass through, and a gate circuit that allows the memory write signal to be applied to a memory write terminal. Since it is constructed with a read/write memory that can be written to when the CPU is running, the probability that the constant data stored in the memory will be destroyed due to CPU runaway is extremely reduced, and the drawbacks of the conventional technology can be largely eliminated. be.

The means for generating the settable signal is connected to a run/setting switch, this running/setting switch is connected to the D input terminal, the CPU's address latch enable signal is connected to the T terminal, and the Q terminal is connected to the gate circuit. Since the CPU is configured with a D flip-flop, even if the operation/setting switch is switched while the CPU is operating, the switch operation at the time of switching will not be valid, and the switched state will become effective from then on.
Therefore, there is an advantage that a half-finished memory write signal is not output.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of the main parts of a conventional microcomputer system, and FIG. 2 is a schematic circuit diagram of an embodiment of the present invention. In the figure, 10 is a RAM memory, 11 is an address bus, 12 is a data bus, 13 is an MEMR signal, 1
4 is MEMW signal, 15 is gate circuit, 16 is D
Flip-flop, 17 is operation/setting switch,
18 is an inverter circuit, and 19 is an ALE signal.

Claims (1)

[Claims] 1 A means for generating a settable signal, a gate circuit that opens upon application of the settable signal and allows a memory write signal to pass through, and a readable and writable memory that becomes writable when the memory write signal is applied to a memory write terminal. Further, the generating means for the settable signal is connected to a run/setting switch, the run/setting switch is connected to the D input terminal, the address latch enable signal of the CPU is connected to the T terminal, and the Q terminal is connected to the D input terminal. A memory protection circuit comprising a D flip-flop connected to a gate circuit.