JPS6257035A - Microprogram processor - Google Patents

Abstract

PURPOSE:To facilitate finding of a microprogram error by providing a means designating an address of a microprogram, a waiting time designation means and a waiting means so as to improve the existence probability of an external asynchronizing signal. CONSTITUTION:A pseudo address of a microprogram is set to a waiting address designation switch 5 and a waiting time is set to a waiting time designation switch 7 in advance. An instruction in the inside of a control storage 1 is executed by a sequential instruction execution circuit 3 attended with the start of execution of the program and when contents of the switch 5 and an instruction address register 2 are coincident, a waiting counter 6 is activated via an address comparison circuit 4. Then, the counter 6 is set equal to a value set to the switch 7, subtraction is conducted at each prescribed time to await the execution of the program and when the content of the counter 6 is zero, the execution is restarted. Thus, the existing probability of the external asynchronizing signal is improved to facilitate the finding of the microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram processing device that easily detects errors occurring in microprograms.

(Prior Art) A microprogram processing device that operates by receiving an external asynchronous signal operates while the microprogram detects an event that occurs asynchronously with the operation of the microprogram. In the processing of such a microprogram, if there is an error in the processing that only passes when an external asynchronous signal is generated while the microprogram is running at a specific address, it would appear to be an intermittent fault on the surface. appears as.

(Problems to be Solved by the Invention) In the above-described conventional microprogram processing device, the above-mentioned intermittent fault appears and the above-mentioned error location is detected. The drawback was that it required a lot of effort.

An object of the present invention is to specify a microprogram address and a waiting time for execution of a microinstruction, and when executing a microinstruction at the specified address, to fully execute the waiting for the specified time, and to set the waiting time to the specified address. It is an object of the present invention to provide a microprogram processing device configured to eliminate the above-mentioned drawbacks by inserting a microprogram, increase the probability of the presence of an external asynchronous signal, and make it easy to discover any errors in the microprogram.

(Means for Solving the Problems) A microprogram processing device according to the present invention is provided with an address specifying means, a wait time specifying means, and a waiting means, and is configured to operate upon receiving an external asynchronous signal. It is.

The addressing means is for specifying the address of the microprogram.

The waiting time designation means is for designating the execution waiting time of a microinstruction included in a microprogram.

The waiting means is for waiting for a time specified by the waiting time specifying means when executing a microinstruction at an address specified by the address specifying means.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microprogram processing device according to the present invention.

In FIG. 1, 1 is a control memory, 2 is an instruction address register, 3 is an instruction execution circuit, 4 is an address comparison circuit, 5 is a queuing address designation switch, 6 is a queuing counter, and 7
8 is a wait time designation switch, 8 is a lock generation circuit for executing instructions, and 9 is an AND gate.

In FIG. 1, among the microprograms stored in the control memory 1', the microinstruction at the address indicated in the instruction address register 2 is read out by the instruction execution circuit 3 and executed.

Further, the contents of the instruction register 2 are changed according to the execution result, and the microprograms are executed sequentially. The address comparison circuit 4 compares the data specified by the queuing address designation switch 5 with the contents of the command address register 2, and outputs an address match signal onto the signal line 4a when the two match. The content of the waiting counter 6 is initialized to O, and when it receives an address match signal on the signal line 4a, it reads the count value set in the waiting time designation switch 7, and then subtracts it at regular intervals. Execute and stop when the value becomes 0. The executable signal on the signal line 6a is a signal that is output while the content of the waiting counter 6 is 0, and is a signal that is output from the lock generation circuit 8 that executes the command on the signal line 8a. 9
and the signal line 8a is gated during the subtraction of the waiting counter 6.
This prevents the lock from being supplied to the instruction execution circuit 3 via the lock.

Next, the operation of the microprogram processing device shown in the first factor will be explained. When evaluating the microprogram, the operator sets the suspect address of the microprogram in the waiting address designation switch 5 and sets the waiting time in the waiting time designation switch 7.

When execution of the microprogram starts, control memory 1
The internal instructions are sequentially executed by the instruction execution circuit 3, and when the contents of the instruction address register 2 match, the address comparison circuit 4 is activated and the waiting counter 6 is excited by the address match signal on the signal line 4a. be done.

At this time, the waiting counter 6 is set to the waiting time designation switch 7.
is set equal to the value set in , and subtraction is performed at regular intervals. During this time, the contents of the counter 6 are other than 0, so no executable signal is output on the signal line 6a.
Since the lock on the signal line 8a is suppressed by the AND gate 9 and no lock is supplied to the n1 instruction failure circuit 3, execution of the microprogram is also deferred. Eventually, when the waiting counter 6 continues to decrement and the content becomes O, the executable signal is output again on the signal line 6a, and the instruction execution circuit 3 starts executing the microprogram.

As described above, the microprogram is executed while waiting for the specified time at the specified address, and the probability that an external asynchronous signal will be generated during the above waiting time increases.

(Effects of the Invention) As explained above, the present invention increases the probability that an external asynchronous signal will be generated when a suspect microprogram address is executed, thereby reducing the effort required to detect program errors in the vicinity of such an address. This has the effect of greatly saving labor and making it easier to evaluate programs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram processing device according to the present invention. 1... Control memory 2... Instruction address register 3... Instruction execution circuit 4... Address comparison circuit 5
. . . Waiting address designation switch 6 . . Waiting counter 7 . . Waiting time designation switch 8 . . . Command execution lock generation circuit 9 . . . AND gates 4a, 6a, 8a . . . Signal line diagram 1

Claims (1)

[Claims] Addressing means for specifying an address of a microprogram, waiting time specifying means for specifying an execution waiting time of a microinstruction included in the microprogram, and a microinstruction at an address specified by the addressing means. A microprogram processing device comprising: a waiting means for waiting for a time specified by the waiting time specifying means during execution, and configured to operate upon receiving an external asynchronous signal.