JPH04131931A - Control system for real address load instruction - Google Patents

Abstract

PURPOSE:To improve the executing speed of a real address load instruction by providing the exception processing firmware for real address load instruction and the instruction processing firmware which sets a condition code showing no occurrence of an exception and completes the execution of the real address load instruction. CONSTITUTION:The exception processing firmware 6 for real address load instruction is provided together with the instruction processing firmware 3 which loads a real address, i.e., the output of a real address conversion means to a base register 9 and sets a condition code showing no occurrence of an exception to complete the execution of the real address load instruction. When no exception occurs in a real address converting process, the real address, i.e., the output of the real address conversion means is loaded to the register 9 and the condition code showing no occurrence of an exception is set. Thus the execution of the real address load instruction is completed. As a result, the executing speed of the real address load instruction is improved when no exception occurs in a real address converting process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides an implementation for controlling the execution of a real address load instruction (an instruction for converting an effective address into a real address and loading the real address into a HAS register) in a data processing device. Related to address load command control method.

[Conventional technology]

Conventionally, in this type of real address load instruction control system, processing as shown in the flowchart of FIG. 3, for example, has been performed.

That is, first, the effective address generation means obtains an effective address from the instruction word of the real address load instruction (step 31).

Next, the instruction processing firmware issues a real address conversion request (a request for conversion from an effective address to a real address) to the memory buffer control unit (hardware that converts an effective address to a real address) (step 32 ).

The instruction specification of the real address load instruction specifies that when an exception (exception condition) occurs during the real address conversion process, a condition code is set according to the type of exception. To this end, the memory buffer control unit issues a reply synchronization microinstruction that reflects the presence or absence of an exception to the exception detection hardware (step 33).
.

When the exception detection hardware receives a reply synchronization microinstruction indicating the occurrence of an exception, it detects the exception type and sets an error code indicating the exception type in the error code register. However, the exception detection hardware
Even when an exception occurs, the control is not switched to the exception processing firmware (firmware that handles exceptions related to various instructions), and the exception generation flip-flop (which has information indicating whether an exception has occurred during the real address conversion process) Information indicating that an exception has occurred in the flip-flop (
``l''). In order to prevent control from being switched to the exception handling firmware in this way, the above-mentioned reply synchronization microinstruction is an exception mask reply synchronization microinstruction, which is a command that suppresses the startup of the exception handling firmware.

Now, the instruction processing firmware refers to the exception occurrence flip-flop and determines whether or not information indicating that an exception has occurred in the real address translation process is set to "1" (step 34).

If it is determined in step 34 that "1" is set in the exception generation flip-flop, the instruction processing firmware determines what type of exception has occurred by referring to the error code register (step 37); The condition code is updated based on the type of exception that has occurred (steps 38 to 40), that is, when a segment fault or a segment table length error is detected, the condition code is updated to "l". (Step 38), if a page table length error is detected, the condition code is updated to "2" (Step 39); if a page fault is detected, the condition code is set to "3". (step 40).

If it is determined in step 34 that the exception occurrence flip-flop is not set to "1" (if no exception occurs during the real address translation process), the instruction processing firmware sets the condition code to "0" (exception Step 35
), loads the real address into the base register (step 36), and ends the execution of the real address load instruction.

[Problem to be solved by the invention]

In the conventional real address load instruction control method described above, although exceptions do not occur most frequently during the real address conversion process, the exception judgment process by the instruction processing firmware (the judgment process at step 34 in FIG. 3) Since this is necessary, there is a drawback that the execution speed of the real address load instruction is reduced.

In view of the above points, an object of the present invention is to provide a real address load instruction control method that can improve the execution speed of a real address load instruction when no exception occurs during the real address conversion process.

[Means to solve the problem]

The real address load instruction control method of the present invention includes a real address load instruction flip-flop that indicates whether or not a real address load instruction is being executed, and an effective address generation means that generates an effective address from the instruction word of the real address load instruction. and a real address conversion means that converts the effective address generated by the effective address generation means into a real address and issues a reply synchronization microinstruction that reflects the occurrence of an exception in the real address conversion process, and this real address conversion means. exception detection hardware that activates exception handling firmware for the real address load instruction when it detects that exception handling is required based on the reply synchronization microinstruction issued by the reply synchronization microinstruction; When information indicating that a load instruction is being executed is set, a condition code corresponding to the exception type of an exception that occurs during the real address conversion process by the real address conversion means is set, and the real address load instruction is executed. exception handling firmware for the real address load instruction to be terminated; and a real address translation request is issued to the real address translation means, and if no exception occurs in the real address translation process by the real address translation means, the real address It has instruction processing firmware that loads the real address that is the output of the conversion means into the Hass register, sets a condition code indicating that no exception has occurred, and terminates execution of the real address load instruction.

[Effect]

In the real address load instruction control method of the present invention, the real address load instruction flip-flop indicates whether or not the real address load instruction is being executed, and the effective address generation means generates an effective address from the instruction word of the real address load instruction. Then, the real address translation means converts the effective address generated by the effective address generation means into a real address, issues a reply synchronization microinstruction that reflects the occurrence of an exception in the real address translation process, and executes the exception detection hardware. When it is detected that exception handling is required based on the reply synchronization microinstruction issued by the address translation means, the exception handling firmware for the real address load instruction is activated, and the exception handling firmware for the real address load instruction When information indicating that a real address load instruction is being executed is set in the flip-flop for the real address, a condition code corresponding to the exception type of the exception that occurred during the real address translation process by the real address translation means is set, and the real address is After the execution of the load instruction is completed, the instruction processing firmware issues a real address translation request to the real address translation means, and if no exception occurs during the real address translation process by the real address translation means, the output of the real address translation means A real address is loaded into the base register, a condition code is set indicating that no exception has occurred, and execution of the real address load instruction is terminated.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the real address load instruction control method of the present invention.

The real address load instruction control method of this embodiment uses a real address load instruction flip-flop 1 that indicates whether or not the real address load instruction is being executed (if it is being executed, rlJ is set; if it is not being executed, rlJ is set; for"
0), effective address generation means 2 generates an effective address from the instruction word of the real address load instruction.
Then, a real address conversion request is issued to the memory buffer control unit 4, and if no exception occurs during the conversion process by the memory buffer control unit 4, the real address output from the memory buffer control unit 4 is sent to the base register 9. The instruction processing firmware 3 to be loaded and the memory buffer control unit (real address conversion means) which is hardware that converts an effective address to a real address and issues a reply synchronization microinstruction that reflects the occurrence of an exception in the real address conversion process. 4, exception detection hardware 5 that activates the exception processing firmware 6 for the real address load instruction when it detects that exception processing is necessary based on the reply synchronization microinstruction issued by the memory buffer control unit 4; Real address load instruction exception handling firmware 6 that executes exception handling regarding the real address load instruction when an exception occurs in the real address conversion process by the buffer control unit 4, an error code register 7, a condition code 8, and a base register. 9.

FIG. 2 is a flowchart showing the processing of the real address load command control method of this embodiment. This process includes an effective address conversion step 21, a real address conversion request issue step 22, and a reply synchronization microinstruction issue step 2.
3, condition code set step 24, base register load step 25, real address load instruction flip-flop determination step 26, exception type determination step 27, condition code "1" set step 28, and condition code r2J. It consists of a theft step 29 and a condition code "3" setting step 30.

Next, the operation of the real address load instruction control system of this embodiment configured as described above will be explained.

First, the effective address generation means 2 obtains an effective address from the instruction word of the real address load instruction (step 21).
.

Next, the instruction processing firmware 3 issues a real address conversion request to the memory buffer control unit 4 (
Step 22).

Note that when a real address load instruction is executed, the instruction code of the instruction word of the real address load instruction is decoded by hardware that decodes various instructions, etc.
"1" is set in the flip-flop 1 for the real address load instruction.

The memory buffer control unit 4 includes the instruction processing firmware 3
Based on the real address translation request from
Convert the effective address obtained in step 1 to a real address, and issue a reply synchronization microinstruction that reflects the occurrence of an exception in the real address conversion process (step 2).
3).

The exception detection hardware 5 verifies whether exception handling is necessary (an exception has occurred during the real address translation process) based on this reply synchronization microinstruction.

If the exception detection hardware 5 verifies that exception handling is unnecessary, the real address load instruction is normally executed. That is, the instruction processing firmware 3
Update the condition code register 8 to "0" (information indicating that no exception has occurred).Step 24
), loads the real address obtained in step 23 into the base register 9 (step 25), and ends the execution of the real address load instruction.

Note that after the processing in step 25 by the instruction processing firmware 3, the real address instruction flip-flop 1 is reset (updated to "0") under hardware control.

When the exception detection hardware 5 verifies that exception handling is necessary based on the reply synchronization microinstruction,
The exception type of the exception is detected, an error code indicating the exception type is set in the error code register 7, and the exception handling firmware 6 for the real address load instruction is activated (in this case, the processes in steps 24 and 25 are not performed). ).

In order to switch control from the exception detection hardware 5 to the exception handling firmware in this way, the reply synchronization microinstruction issued in step 23 is a command that does not prevent the exception handling firmware from starting. 7 criply synchronous microinstructions.

The exception handling firmware 6 for the real address load instruction is
It is determined whether "1" is set in the flip-flop l for the real address load instruction (step 26).

If it is determined in step 26 that "1" is set in the flip-flop 1 for the real address load instruction (when the real address load instruction is being executed), the exception handling firmware 6 for the real address load instruction handles the error. Refer to the code register 7 to determine the type of exception (step 27), and set the condition code in the condition code register 8 as specified in the instruction specification according to the exception type (steps 28 to 3).
0), that is, when a segment fault is detected or a segment table length error is detected, the condition code is updated to "1" and the condition code register 8 is set to "1".
8) If a page table length error is detected, update the condition code to "2" Step 29)
If a page fault is detected, the condition code is updated to "3" (step 30).

Note that if "1" is not set in the flip-flop 1 for the real address load instruction in step 26 (when the real address load instruction is not being executed and the flip-flop 1 for the real address load instruction is set to "0"). )
In this case, the exception handling firmware 6 for the real address load instruction passes control to the normal exception handling firmware.

〔Effect of the invention〕

As explained above, the present invention improves the execution speed of the real address load instruction when no exception occurs during the real address conversion process by providing a flip-flop for the real address load instruction and exception handling firmware for the real address load instruction. The effect is that it can be improved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the configuration of an embodiment of the present invention, FIG. 2 is a flowchart showing the processing of the real address load instruction control method shown in FIG. 1, and FIG. 3 is a flowchart showing processing of an example of a control method. In the figure, 1...Flip-flop for real address load instruction, 2...Effective address generation means, 3...Instruction processing firmware, 4...Memory buffer control unit, 5...Exception detection hardware, 6...Exception handling firmware for real address load instruction, 7...Error code register, 8...Condition code register, 9...Heas register. First cause

Claims (1)

[Scope of Claims] A flip-flop for a real address load instruction that indicates whether or not a real address load instruction is being executed; an effective address generating means for generating an effective address from the command word of the real address load instruction; a real address conversion means that converts an effective address generated by the generation means into a real address and issues a reply synchronization microinstruction that reflects the occurrence of an exception in the real address conversion process; and a reply issued by the real address conversion means. Exception detection hardware that activates exception handling firmware for a real address load instruction when it detects that exception handling is required based on a synchronous microinstruction; and The real address sets a condition code corresponding to the exception type of an exception that occurs in the real address translation process by the real address translation means and terminates execution of the real address load instruction when information indicating that the real address is translated is set. load instruction exception processing firmware; and when a real address translation request is issued to the real address translation means and an exception does not occur during the real address translation process by the real address translation means, the output of the real address translation means is A real address load instruction control method comprising: instruction processing firmware that loads a certain real address into a base register, sets a condition code indicating that no exception has occurred, and terminates execution of the real address load instruction.