JPH05241820A - Microprogram controller - Google Patents

Abstract

PURPOSE:To provide a microprogram controller by which a CPU processing time can be shortened by reducing the firmware processing step of a floating point arithmetic mechanism or the like. CONSTITUTION:This device is equipped with a converting part 14 which prepares the read address of a control ROM 13 from an FPU micro instruction after an execution, a selector 15 which selects a lead address to the control ROM 13 included in the micro instruction read from a micro instruction ROM 11, or the output of the converting part 14 as the valid read address of the control ROM 13. Thus, the read address of the control ROM 13 except the leading address can be directly decided from the FPU micro instruction after the execution, so that the CPU processing time can be shortened by reducing the FPU firm ware processing step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro program controller, and more particularly to a micro program controller for executing a firmware of a floating point arithmetic unit under the control of a CPU firmware in a pie blind system.

[0002]

2. Description of the Related Art Conventionally, an instruction execution process under microprogram control employing a pie-line control system has been
As shown in FIG. 3, A (address operation) -stage, C
(Cache access) -stage, E (execution) -stage. At the A-stage, the address of the data cache or the control memory is determined from the instruction code indicated by the software instruction or the executed micro instruction. In the C-stage, the determined address is used to access the data cache and read the micro instruction from the control memory. In the C-stage, the instruction is executed based on the read micro instruction.

In such a pipe line control system,
FIG. 4 shows the configuration when operating the floating point arithmetic unit (FPU firmware) under the control of the CPU firmware.
Shown in. In the figure, 1 is a micro program ROM storing CPU firmware, 2 is a micro instruction register for temporarily holding micro instructions read from the micro program ROM 1, 3 is a control ROM storing FPU firmware, and 4 is a control ROM 3. It is an FPU microinstruction register that temporarily holds the microinstruction read by more. The micro program RO
In addition to the CPU firmware, the read address for the control ROM 3 is stored in M1.

In this structure, the microprogram R
From OM1, the address A1 determined in the A-stage
The microinstruction M1 at the location designated by is read and held in the microinstruction register 2.

Here, when the held micro instruction is related to the execution of a normal CPU instruction, a control signal C is given to each functional unit to execute the CPU firmware processing. At this time, the read address of the next microprogram ROM 1 is determined from the address section A1 of the microinstruction held in the microinstruction register 2 to the A-stage, and the next processing is performed.

In addition, control RO is applied to the micro instruction register 2.
When the read address A3 for M3 is held, the corresponding microinstruction M2 is read from the control ROM 3 based on this address A3 and held in the FPU microinstruction register 4. As a result, the FPU firmware processing is executed. At this time, the next microprogram RO is executed from the address section A4 of the microinstruction held in the FPU microinstruction register 4 to the A-stage.
The address A1 of M1 is determined and the following processing is performed.

As described above, the reading of the micro instruction from the control ROM 3 is executed based on the address A3 read from the micro program ROM 1. Therefore, as shown in FIG. 5, execution of an instruction by the FPU firmware always requires an extra step until it is started by the instruction by the CPU firmware, and is not started until the second step of the E-stage. Was there.

[0008]

SUMMARY OF THE INVENTION The present invention is intended to solve such a problem, and a micro program control device capable of reducing the CPU processing time by reducing the firmware processing steps of the floating point arithmetic unit and the like. Is intended to be provided.

[0009]

In order to achieve the above-mentioned object, a microprogram control device of the present invention comprises a first storage means for storing a first microprogram and a first storage means.
Second storage means that stores a second microprogram that operates under the control of the microprogram, and address determination means that determines a read address for the first storage means based on a software instruction or a microinstruction after execution. A means for reading the corresponding microinstruction from the first storage means based on the address determined by the address determination means, and a conversion for converting the address determined by the address determination means into a read address for the second storage means. Means, selecting means for selecting either the address in the microinstruction read from the first storing means or the conversion result of the converting means as a valid read address for the second storing means, and the selecting means. Based on the read address, the corresponding micro instruction is read from the second storage means. And and means for.

[0010]

In the microprogram controller of the present invention, first, the address determining means determines the read address for the first storing means from the instruction code indicated by the software instruction. Based on this address, the corresponding micro instruction is read from the first storage means. Here, when the start address of the second microprogram is indicated in the microinstruction, the start address is selected by the selection means as a valid read address for the second storage means. As a result, the first microinstruction is read from the second storage means and the second microprogram is executed. After that, the address determined by the address determining means based on the executed microinstruction is converted into the read address for the second storage means by the converting means. Then, this address is selected by the selection means as a valid read address for the second storage means.

In this way, the read address other than the start address for the second storage means can be directly determined from the executed micro instruction, and the firmware processing steps such as the floating point arithmetic mechanism can be reduced to shorten the CPU processing time. Can be realized.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microprogram control device adopting a pipeline control system according to an embodiment of the present invention.

In the figure, reference numeral 11 is a microprogram ROM which stores CPU firmware which is a first microprogram. 12 is A (address calculation)-
Micro program R based on the address obtained at the stage
It is a microinstruction register that temporarily holds the microinstruction read from the OM 11. Reference numeral 13 is a control ROM that stores a floating point arithmetic unit firmware (FPU firmware) that is a second microprogram that operates under the control of the CPU firmware. 14 is included in the micro instruction read from the control ROM 13,
It is a conversion unit that converts the next read address for the microprogram ROM 11 into a read address for the control ROM 13. Reference numeral 15 is a selector for selecting one of the read address for the control ROM 13 and the output of the conversion unit 14 included in the microinstruction held in the microinstruction register 12 as an effective read address of the control ROM 13. Reference numeral 16 is an FPU microinstruction register that temporarily holds the FPU microinstruction read from the control ROM 13. Although not shown in the drawing, the microprogram ROM 11 and the control R are provided in this device.
There is a storage controller as a means for reading a target microinstruction from the OM 13 based on each address and for executing other necessary control. In addition to the CPU firmware, the microprogram ROM 11 stores the start address of the control ROM 13.

Next, the operation of this embodiment will be described.

First, the read address A1 of the microprogram ROM 11 is determined at the A (address operation) -stage from the instruction code indicated by the software instruction. Then, from the microprogram ROM 11,
The microinstruction M1 at the location indicated by the address determined in the stage is read and held in the microinstruction register 12.

Here, when the microinstruction held in the microinstruction register 12 is related to the execution of a normal CPU instruction, the control signal C1 is given to each functional unit to execute the CPU firmware processing. At this time, the address A1 of the next microprogram ROM 11 is determined from the address portion A2 in the microinstruction held in the microinstruction register 12 at the A-stage, and the next processing is performed.

In addition, control R is applied to the micro instruction register 12.
When the start address A3 of the OM 13 is held, the first F from the control ROM 13 is based on this start address A3.
The PU micro instruction M2 is read and held in the FPU micro instruction register 16. That is, at this time, the selector 15 selects the address A3 held in the micro instruction register 12 as a valid address. As a result, the FPU firmware processing is executed. At this time, the F held in the FPU micro instruction register 16
Address A1 of the next micro program ROM 11 at the A-stage from the address section A4 in the PU micro instruction
Is determined.

From the next processing, the result A5 of code conversion of the address A1 by the conversion unit 14 is stored in the control ROM 13
Is selected by the selector 15 as a valid read address of. After this, similarly, control RO is performed based on this address A5.
The corresponding FPU micro instruction is read from M13 and held in the FPU micro instruction register 16. As a result, the next FPU firmware process is executed.

FIG. 2 is a diagram showing the effect of this embodiment.
As described above, according to this micro program controller, the execution of the first FPU micro instruction in the control ROM 13 is started from the second step of the E-stage as before, but the subsequent FPU micro instructions are executed. Starts from the first step of the E-stage, as shown. Therefore, the processing by the FPU firmware is similar to the CPU firmware processing.
It can be executed efficiently.

[0021]

As described above, according to the microprogram controller of the present invention, the read address other than the start address for the second storage means can be directly determined from the executed microinstruction, and the floating point The CPU processing time can be shortened by reducing the firmware processing steps such as the arithmetic mechanism.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a micro program control device adopting a pipeline control system according to an embodiment of the present invention.

FIG. 2 is a block diagram of F in the microprogram controller of FIG.
It is a figure which shows the execution process of PU instruction.

FIG. 3 is a diagram showing an instruction execution process under microprogram control adopting a conventional pipeline control method.

FIG. 4 is a block diagram showing a configuration of a conventional micro program control device.

FIG. 5: F in a conventional micro program controller
It is a figure which shows the execution process of PU instruction.

[Explanation of symbols]

11 ... Micro program ROM, 12 ... Micro instruction register, 13 ... Control ROM, 14 ... Conversion unit, 15 ... Selector, 16 ... FPU micro instruction register.

Claims (1)

[Claims] 1. A first storage means for storing a first microprogram, and a second storage device which operates under the control of the first microprogram.
Second storing means for storing the micro program, address determining means for determining a read address for the first storing means based on the software instruction or the executed micro instruction, and the address determined by the address determining means. Means for reading the corresponding microinstruction from the first storage means based on the above, conversion means for converting the address determined by the address determination means into a read address for the second storage means, and Selecting means for selecting either the address in the microinstruction read from the storing means or the conversion result of the converting means as a valid read address for the second storing means; and the read address selected by the selecting means. Based on this, the corresponding micro instruction is read from the second storage means. Microprogram control apparatus characterized by comprising a stage.