WO2010029682A1

WO2010029682A1 - Information processing device

Info

Publication number: WO2010029682A1
Application number: PCT/JP2009/003710
Authority: WO
Inventors: 中谷浩晃; 山田哲也; 加藤直樹
Original assignee: 株式会社ルネサステクノロジ
Priority date: 2008-09-10
Filing date: 2009-08-04
Publication date: 2010-03-18
Also published as: EP2328075A1; US20110238883A1; CN102150132A; EP2328075A4; JPWO2010029682A1

Abstract

It is possible to execute a bit operation without lowering the bus performance. An information processing device (10) includes CPUs (101, 102) which can fetch and execute a command and peripheral modules (M1, M2, M3) each having a built-in register which can be rewritten by the CPUs and connected to the CPUs by a bus. The CPUs have a function to issue a bus command for instructing a write operation in the bit unit into the registers contained in the peripheral modules so as to execute the bit operation command fetched by the CPUs. When the bus command is issued, the peripheral modules execute the write operation in the bit unit into the registers. Thus, after the bus command is issued, the CPUs need not lock the bus. That is, it is possible to execute the bit operation without lowering the bus performance.

Description

Information processing device

The present invention relates to a bit operation of a register included in a peripheral module coupled to an information processing apparatus, particularly a CPU (central processing unit).

The information processing apparatus includes a microprocessor, a microcontroller, a signal processor, an image processor, and a sound processor. A microprocessor, which is an example of an information processing device, shortens data access time from a CPU to each peripheral module in a chip in order to perform bit manipulation processing, which is one of data processing inside a semiconductor chip, at high speed. There is a need. In order to shorten the access time, it is widely performed to improve the operating frequency of the microprocessor, increase the speed of the bus to which each peripheral module in the chip is connected, and add a new instruction for bit manipulation.

However, a microprocessor has conventionally been configured to process data in a certain unit (8 bits / 16 bits / 32 bits) with respect to peripheral registers, memories, etc., and a bit operation for operating only one bit is directly performed by a peripheral module. I can't tell you. For this reason, when performing bit operations, data is once read into the CPU from a peripheral register or memory in a certain unit (8 bits / 16 bits / 32 bits), and only one bit in the read data is changed, A read-modify-write (hereinafter abbreviated as “RMW”) operation for writing back to the peripheral module again is required.

However, during this RMW operation, the CPU locks the bus (fixes the bus to a state that does not accept other than bit manipulation processing), and the CPU itself cannot execute other instructions during RMW. For this reason, a bit manipulation method that shortens the bit manipulation processing and does not require an RMW operation is required so that the CPU can execute other instructions.

As such a bit operation method that does not require an RMW operation, a method as described in Patent Document 1 can be cited. In Patent Document 1, in order to increase the bit operation speed, a memory address area is added in order to allocate a 32-bit address for each bit to be operated, and a normal instruction (write instruction) is added to the added memory address area. A technique is disclosed in which a desired bit operation can be performed when data is written. By writing data to the additional memory address area in a certain unit (8 bits / 16 bits / 32 bits), there is no need to read the data into the CPU for modification, that is, no RMW operation is required in the CPU, and bit manipulation is performed. The speed can be increased. Further, since the additional memory address area is accessed with a normal instruction, there is no need to add a new instruction for bit manipulation.

US Patent Application Publication No. 2005/0177791

As described above, in Patent Document 1, a memory address area having a certain bit width (8 bits / 16 bits / 32 bits) is added for bit manipulation, and a normal instruction (8 bits / 16 bits) is added to the memory address area. A method is disclosed in which, when data is written in units of / 32-bit units), a LSU (load store unit) converts a write operation into an RMW operation and performs a bit operation. According to this, since the bit operation is performed by the LSU, the CPU only has to write data in the added memory address area, and the execution time of the bit operation processing of the CPU is shortened.

However, in this method, since the bit operation is performed from the CPU to the LSU and the LSU performs the RMW operation, the processing time of the bit operation itself for the peripheral modules is not shortened. Further, in a CPU or the like equipped with a plurality of cores, it is necessary to lock the bus during the RMW operation in order to prevent rewriting of data due to an instruction from another core during the RMW operation. Since the CPU can perform a bit operation only with a normal instruction, it can execute another instruction without waiting for the completion of the RSU RMW operation. However, while the LSU is executing the RMW operation, Since it is necessary to lock the bus, the performance of the bus may be reduced.

An object of the present invention is to provide a technique for performing a bit operation without degrading bus performance.

Another object of the present invention is not to add a memory address area but to add a new bus command (1-bit write operation command) and connect a bus state controller for controlling peripheral modules connected to the external address space. The purpose is to provide a technology for speeding up the bit operation by grasping the module bus command support / non-support status, switching between the new bus command and the old bus command.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

A typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the information processing apparatus includes a CPU that can fetch and execute an instruction, and a peripheral module that includes a register that can be rewritten by the CPU and is coupled to the CPU by a bus. The CPU includes a function of issuing a bus command for instructing a bit-unit write operation to a register included in the peripheral module in order to execute the fetched bit manipulation instruction. When the bus command is issued, the peripheral module performs a bit-by-bit write operation on the register. This eliminates the need for the CPU to lock the bus after issuing the bus command. This allows bit operations to be performed without degrading the bus performance.

The following is a brief description of the effects obtained by the representative inventions disclosed in the present application.

That is, according to the present invention, bit operations can be performed without degrading bus performance. In addition, a new bus command is added, and the bus state controller switches between the new bus command and the old bus command to perform bit operations, so even if modules compatible with the old and new bus commands are mixed, it is possible to speed up bit operations. .

FIG. 1 is an explanatory diagram of a bus command switching type bit operation in a microcomputer as an example of an information processing apparatus according to the present invention. FIG. 2 is a block diagram illustrating a configuration example of the microcomputer. FIG. 3 is a block diagram showing a configuration example of the bus state controller in the microcomputer. FIG. 4 is a block diagram illustrating a configuration example of the command determination controller in the bus state controller. FIG. 5 is a block diagram showing a configuration example of functional modules corresponding to the new bus command BC1 in the microcomputer. FIG. 6 is a flowchart of the bit operation in the microcomputer. FIG. 7 is an explanatory diagram of a bit operation example of the module corresponding to the new bus command BC1 and the non-corresponding module.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] An information processing apparatus (10) according to a typical embodiment of the present invention includes a CPU (101, 102) that can fetch and execute an instruction and a register that can be rewritten by the CPU. The CPU includes peripheral modules (M1, M2, M3) coupled by a bus. The CPU includes a function of issuing a bus command for instructing a bit-unit write operation to a register included in the peripheral module in order to execute the fetched bit manipulation instruction.

When the bus command is issued, the CPU executes a bit unit write operation on the register in the peripheral module. For this reason, after the bus command is issued, it is not necessary to lock the bus, so that bit operations can be performed without degrading the performance of the bus.

[2] In the above [1], the peripheral module includes a bit operation controller that executes a write operation in bit units for the register in response to the bus command issued from the CPU.

[3] The information processing apparatus (10) includes a CPU (101, 102) capable of issuing a bus command for instructing a write operation in bit units when executing a fetched instruction, and the CPU is a bus And peripheral modules (M1, M2, M3) coupled together. The peripheral module includes a register (52) that can be rewritten by the CPU and a bit operation controller (51) that executes a write operation in bit units for the register in response to the bus command.

[4] In [3], the bus command issued from the CPU may be transmitted to the bit manipulation controller via the bus.

[5] In the above [3], the bus command issued from the CPU can be transmitted to the bit operation controller via a dedicated line. When a dedicated line is used, a bus command can be transmitted at a higher speed than when a bus is used.

[6] The information processing apparatus (10) includes a CPU (101, 102) capable of issuing a bus command for instructing a write operation in bit units when executing a fetched instruction, and the CPU is a bus The peripheral modules (M1, M2, M3) coupled by the above-mentioned bus and the bus state controller (105) coupled to the bus and performing the bus state control. The bus state controller has a first circuit (31) that makes it possible to identify whether or not the peripheral module supports the bus command, and a format in which the peripheral module supports the first bus command from the CPU. A second circuit (32) that can be converted into a second bus command, a first bus command transmitted from the CPU based on an identification result in the first circuit, and a second bus output from the second circuit And a third circuit (33) capable of selectively outputting a command to the peripheral module.

The bus state controller receives the first bus command from the CPU, and determines whether to output the first bus command or convert the first bus command into the second bus command. As a result, the CPU only needs to output the first bus command of the 1-bit write operation. Even if the bus state controller outputs the second bus command and the RMW operation occurs, the CPU waits for the completion of the RMW operation. Since other instructions can be executed, bit operations can be performed without degrading the performance of the bus.

[7] In the above [6], when the bus command converted by the second circuit is output via the third circuit, the second circuit reads data from the peripheral module and reads the read data Then, RMW is performed to write back to the peripheral module again.

2. Next, the embodiment will be described in more detail.

FIG. 2 shows a microcomputer as an example of an information processing apparatus according to the present invention. A microcomputer 10 shown in FIG. 2 includes a plurality of

CPUs

101 and 102, a bus state controller (BSC) 105, and a plurality of peripheral modules (Modules) M1, M2, and M3. Single-crystal silicon is manufactured by a known semiconductor integrated circuit manufacturing method. It is formed on one semiconductor substrate such as a substrate. The

CPUs

101 and 102 are coupled to the first bus 103, and the peripheral modules M1, M2, and M3 are coupled to the second bus 104. The first bus 103 and the second bus 104 are coupled via a bus state controller 105. An external memory 20 is disposed outside the microcomputer 10. The external memory 20 includes a peripheral module M4. Each of the

CPUs

101 and 102 fetches an instruction from a program memory (not shown) and executes it. Each of the peripheral modules M1, M2, M3, and M4 has a predetermined function.

Next, the bus command switching type bit operation in the microcomputer 10 having the above configuration will be described.

FIG. 1 schematically shows a bus command switching type bit operation in the microcomputer 10 shown in FIG.

In the bus command switching type bit operation in the microcomputer 10 having the above configuration, the

CPUs

101 and 102 output the new bus command BC1 (first bus command) to the bus state controller 105, and the bus state controller 105 outputs a new bus command for each peripheral module. The bit operation is performed by determining the correspondence / non-correspondence and switching between the new bus command and the old bus command (second bus command). According to this operation method, even if a peripheral module connected to the bus includes a new bus command compatible module and a new bus command non-compatible module, the bit operation can be executed. For convenience of explanation, it is assumed that the peripheral modules M1 and M2 correspond to both the new bus command BC1 and the old bus command BC2, and the peripheral modules M3 and M4 correspond only to the old bus command BC2. For the new bus command (BC1) compatible modules M1 and M2, the bit operation can be speeded up as described below, and for the new bus command non-compatible module, the bus state controller 105 receives the new bus command BC1. Is converted into the old bus command BC2, and the RMW operation conventionally performed by the CPU is executed. That is, the

CPUs

101 and 102 can execute a bit operation only by issuing a new bus command BC1 to the bus state controller 105, and can execute other instructions immediately after the new bus command BC1 is output. . Further, since the new bus command corresponding modules M1 and M2 can perform a 1-bit write operation instead of an RMW operation, the bit operation itself can be speeded up.

Here, the bus command is a bit unit (for example, 8 bits or 10 bits) issued to the peripheral module by the instruction interpretation module (decoder) in the CPU in order to execute the instruction fetched by the

CPUs

101 and 102. Etc.). For example, the

CPU

101 or 102 reads an instruction from a program memory (not shown) in which a bit operation instruction is stored, and interprets the instruction with a decoder in the CPU. This decoder outputs a bus command such as read or write, which is an instruction for instructing the peripheral module to perform the operation of the peripheral module necessary for executing the bit manipulation instruction after interpreting the instruction. The bus command is input from the

CPU

101 or 102 to the peripheral module via the dedicated line or the

buses

103 and 104. When a dedicated line is used, a bus command can be transmitted faster than when the

buses

103 and 104 are used.

The proposed new bus command BC1 (first bus command) is an extension of the old bus command BC2 (second bus command). The old bus command BC2 includes read and write as described above. However, the old bus command BC2 is a command for instructing reading or writing in units of bytes or words, and is not a command for instructing writing in units of 1 bit. On the other hand, the new bus command BC1 is a command for instructing a write operation in 1-bit units.

There are two ways to embed bit manipulation information and bit manipulation information. The first is a method of embedding in an empty area of data. In this method, the data access unit is a byte or word unit, and the write unit is a 1-bit unit. For example, a new bus command is a command for accessing data in units of bytes and operating only one bit in the byte data. The bit position of the bit operation and the bit operation information at this time are embedded in the upper free bits of the data.

The second method is to add bit position information and bit operation information to the bus command. The first method embeds bit position information and bit operation information in the upper free bits of data, so the data access unit is limited to byte units or word units. However, since the second method adds operation bit position information and bit operation information to the bus command, the data access unit can be set to other than bytes and words.

In the bus command switching type bit operation in the present embodiment, the bus state controller 105 outputs the new bus command BC1 received from the CPU as it is and executes a 1-bit write operation in order to realize a high bit operation speed, or The new bus command BC1 is converted into the old bus command BC2 and output, and the RMW operation is executed. Here, the configuration and operation of the bus state controller 105 will be described with reference to FIG.

FIG. 3 shows a configuration example of the bus state controller 105.

As shown in FIG. 3, the bus state controller 105 has the following four peripheral modules. That is, a command determination controller (CJC) 31, an RMW module (RMW_Mod) 32, a bus command selector (BC_SEL) 33, and a data selector (D_SEL) 34.

The command determination controller 31 determines whether the new bus command received from the

CPUs

101 and 102 is new bus command supported / not supported for each new bus command supported module and new bus command not supported module connected to the bus. It has a function of determining whether to output a bus command as it is or to convert a new bus command into an old bus command and output it.

The RMW module 32 executes the output of the old bus command BC2 and the RMW operation when the command determination controller 31 determines to output the old bus command.

The bus command selector 33 uses the new bus command BC1 output from the command determination controller 31 and the old bus command BC2 output from the RMW module 32 as a BC2_SEL (old bus command selection signal) signal output from the RMW module 32. Select with.

The data selector 34 selects whether to output the data (DATA) from the

CPUs

101 and 102 as it is or to output the DATA_RMW from the RMW module 32 using BC2_SEL output from the RMW module 32.

The command determination controller 31 receives the new bus command BC1 and the address ADR from the

CPUs

101 and 102, outputs BC1 as it is, and registers the register group I_Reg having new bus command support / non-support information for each peripheral module in the command determination controller 31. Based on the information, if the operation target module is a module that does not support the new bus command, the access unit information B / W of the old bus command BC2 and the old bus command enable signal BC2_EN are output to the RMW module 32.

The RMW module 32 receives an address (ADR) and data (DATA) from the

CPUs

101 and 102, an old bus command enable signal BC2_EN and access unit information B / W from the command determination controller 31, and an old bus command BC2 and an old bus command selection signal. BC2_SEL is output and RMW operation is performed. Although not particularly limited, the RMW module 32 includes a BC2 output control unit B_CNT and three data holding registers Reg_A, Reg_BC, and Reg_D. The BC2 output control unit B_CNT receives the old bus command enable signal BC2_EN and the access unit information B / W from the command determination controller 31, receives the old bus command BC2 to the bus command selector 33, and the old bus command selection signal BC2_SEL to the bus command selector 33. Output to the data selector 34. The three data holding registers Reg_A, Reg_BC, and Reg_D are for preventing a change in bus command / address and data change by data (DATA) from the

CPUs

101 and 102 during the RMW operation. That is, the address holding register Reg_A is for holding the address (ADR) received from the

CPUs

101 and 102 during the RMW operation. The register group Reg_BC is used to hold the old bus command enable signal BC2_EN and the access unit information B / W. That is, the old bus command enable signal BC2_EN and the access unit information B / W received from the command determination controller 31 can be held during the RMW operation. The data holding register Reg_D is used during the RMW operation. This is because when data received from the CPU is written to the connection module, the data is read once in a certain unit (8 bits / 16 bits / 32 bits) and used when a change is made, and from the

CPUs

101 and 102 during the RMW operation. This is to prevent new data (DATA) from being input.

FIG. 4 shows a configuration example of the command determination controller 31 in FIG. As described above, the command determination controller 31 receives the new bus command BC1 and the address (ADR) from the

CPUs

101 and 102, and outputs the new bus command BC1 as it is. Based on the information of I_Reg, the access unit information B / W and the old It is determined whether to output the bus command enable signal BC2_EN. The new bus command BC1 is divided into a path that passes through the command determination controller 31 and a path that is input to the BC2 control unit BC2_CTL. The address (ADR) is input to the decoder DEC, and the output signal ADR_DEC of the decoder DEC is input to the register group I_Reg (R_M1, R_M2, R_M3, R_M4 in the drawing). The decoder DEC recognizes which connection module is accessed from, for example, certain 2-bit information of the address (ADR), and outputs the information to the register group I_Reg. In this register group I_Reg, the connection module has new bus command support / non-support information.

Here, for example, a case where the peripheral module M3 does not support the new bus command (R_M3: 0 in the figure (1 means new bus command supported, 0 means new bus command not supported)) will be described.

When the peripheral module M3 is selected by the address ADR and the output signal ADR_DEC of the decoder DEC is input to the register group I_Reg, it is determined whether or not the new bus command is supported. In the register R_M3, information indicating that the new bus command is not supported (data of 0 is held) is written, so that BC2_CTL_EN (old bus command control unit enable signal) is enabled. The BC2 control unit BC2_CTL outputs the old bus command enable signal BC2_EN and the access unit information B / W since BC2_CTL_EN is enabled.

FIG. 5 shows a configuration example of the functional module M1 corresponding to the new bus command BC1.

As shown in FIG. 5, the functional module M1 includes a function setting register 52 for the functional module and a bit operation controller 51 for performing bit operations on the register 52. Although not particularly limited, the functional module M1 is provided with a bit operation controller (not shown) corresponding to the old bus command in order to support the old bus command BC2. The internal bit manipulation controller 51 receives the new bus command BC1 from the bus state controller 105 and performs an operation of manipulating only one bit. FIG. 5 shows an example in which the second bit of the 32-bit register is operated as an example. As described above, the functional module M1 receives the new bus command BC1 from the bus state controller 105, and operates 1 bit and 2nd bit (bits indicated by hatching) in the 32-bit register. By this operation, 1 bit in the 32-bit register is rewritten.

FIG. 6 shows a flowchart of the above bit operation.

First, a new bus command BC1 is input to the bus state controller 105 (S1: Bus Command BC1 Input). The bus state controller 105 determines whether or not the new bus command is supported (S2: Command Select). When the bus state controller 105 supports the new bus command BC1 (Write), the new bus command BC1 is output (S3: Bus). If the command does not correspond to the new bus command BC1 (Read Modify Write), the new bus command BC1 is converted to the old bus command BC2.

When outputting the new bus command BC1, write 1 bit of the connection module and move to the end of bit operation determination.

When converting the new bus command BC1 to the old bus command BC2, the register is read in units of access unit information B / W (S6: Register Read B / W), and 1 bit is changed (S7: 1 Bit Modify). The access unit information B / W unit is written in the register (S8: Register Write B / W), and the process proceeds to the bit operation end determination (S5: Bit Operation Select).

In the bit operation end determination, if the bit operation is not ended, the new bus command BC1 is returned to the processing (S1) input to the bus state controller 105. If the bit operation is ended, the processing according to this flowchart is performed. Ended (End).

FIG. 7 shows a bit operation example of the new bus command BC1 compatible module and the non-compatible module.

In the case of the module corresponding to the new bus command BC1, as shown in FIG. 7A, only the corresponding 1 bit is rewritten in the module corresponding to the new bus command BC1, whereas in the module not supporting the new bus command BC1 As shown in FIG. 7B, a bus state controller (BSC) 105 is interposed, and the bus state controller (BSC) 105 performs 1-bit rewriting by RMW.

According to the above example, the following effects can be obtained.

(1) When the bus state controller 105 receives a new bus command from the CPU and determines whether to output a new bus command or convert a new bus command into an old bus command, The bus state controller 105 performs an operation of executing the RMW executed by the CPU. Thus, the

CPUs

101 and 102 only need to output a new bus command for a 1-bit write operation. Even if the bus state controller 105 outputs an old bus command and an RMW operation occurs, it does not wait for the completion of the RMW operation. Other instructions can be executed.

(2) Due to the effect (1), the processing efficiency of the microcomputer 10 can be improved.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

In the above description, the case where the invention made by the present inventor is applied to the microcomputer, which is the field of use behind it, has been described, but the present invention is not limited thereto.

The present invention can be applied to a microcontroller, a signal processor, an image processor, an audio processor, and the like.

DESCRIPTION OF SYMBOLS 10 Microcomputer 20 External memory 31 Command determination controller 32 RMW module 33 Bus command selector 34 Data selector 51 Bit operation controller 52 Register 101,102 CPU
105 Bus state controller 103 1st bus 104 2nd bus M1, M2, M3, M4 Peripheral module

Claims

A CPU capable of fetching and executing instructions;
A register rewritable by the CPU, and a peripheral module coupled to the CPU by a bus;
The CPU includes a function of issuing a bus command for instructing a bit-unit write operation to a register included in the peripheral module in order to execute the fetched bit manipulation instruction. Processing equipment.
The information processing apparatus according to claim 1, wherein the peripheral module includes a bit operation controller that executes a write operation in units of bits with respect to the register in response to the bus command issued from the CPU.
A CPU capable of issuing a bus command for instructing a write operation in units of bits when executing the fetched instruction;
The CPU includes peripheral modules coupled by a bus,
The peripheral module includes a register rewritable by the CPU,
An information processing apparatus comprising: a bit operation controller that executes a write operation in units of bits with respect to the register in response to the bus command.
4. The information processing apparatus according to claim 3, wherein the bus command issued from the CPU is transmitted to the bit operation controller via the bus.
4. The information processing apparatus according to claim 3, wherein the bus command issued from the CPU is transmitted to the bit operation controller via a dedicated line.
A CPU capable of issuing a first bus command for instructing a write operation in units of bits when executing a fetched instruction;
A peripheral module coupled to the CPU by a bus;
A bus state controller coupled to the bus for performing bus state control,
The bus state controller includes a first circuit that enables identification of whether the peripheral module supports the bus command;
A second circuit capable of converting the first bus command from the CPU into a second bus command supported by the peripheral module;
A third circuit capable of selectively outputting the first bus command transmitted from the CPU and the second bus command output from the second circuit to the peripheral module based on the identification result in the first circuit. An information processing apparatus comprising:
When the bus command converted by the second circuit is output via the third circuit, the second circuit reads data from the peripheral module, changes a part of the read data, and then again. The information processing apparatus according to claim 6, wherein a read modify write is performed to write back to the peripheral module.