JPS61233838A - Information processor - Google Patents

Information processor

Info

Publication number
JPS61233838A
JPS61233838A JP7483885A JP7483885A JPS61233838A JP S61233838 A JPS61233838 A JP S61233838A JP 7483885 A JP7483885 A JP 7483885A JP 7483885 A JP7483885 A JP 7483885A JP S61233838 A JPS61233838 A JP S61233838A
Authority
JP
Japan
Prior art keywords
task
task change
task switching
instruction
machine language
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7483885A
Other languages
Japanese (ja)
Inventor
Naoya Ono
直哉 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7483885A priority Critical patent/JPS61233838A/en
Publication of JPS61233838A publication Critical patent/JPS61233838A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the overhead of task change by inserting a special machine language instruction to a part of a machine language instruction program where task change is possible with a comparatively small overhead. CONSTITUTION:The machine language instruction representing a task change chance designation instruction is inserted to a part in the program where the overhead for task change is less. When the machine language instruction fed to a decode circuit 1 read in this way is the task change chance designation instruction, it is decoded and a coincidence signal is fed to a task change start circuit 3. The task change start circuit 3 checks whether or not a task change request is stored in a task change request holding circuit 2 in response to the supply of the coincidence signal and when the request is held, a task change start signal is generated to start the task change processing. On the other hand, when not held, no task change start signal is raised and the program execution is transferred to an instruction next to the task change chance designation instruction.

Description

【発明の詳細な説明】 特に複雑な内部状態を有する大型コンビエータ。[Detailed description of the invention] Large comviators with particularly complex internal conditions.

スーパーコンビ島−夕あるいはベクトルプロセッサにお
けるタスク切換え万丈に関する。
Super Combi Island - Concerning task switching in a vector processor.

(従来の技術とその問題点) 一台の情報処理装置において複数のタスクを実行させる
マルチタスキング手法は、従来一般に行われており、こ
れに工り情報処理装置の使用効率を向上できることが知
られている。(@″電子計算機(1) ’金田弘著、コ
ロナ社、147−151 頁、昭和45年)。
(Conventional technology and its problems) Multitasking methods, in which a single information processing device executes multiple tasks, have been commonly used in the past, and it is known that this technique can improve the efficiency of using the information processing device. It is being (@"Electronic Computer (1)' by Hiroshi Kaneda, Corona Publishing, pp. 147-151, 1971).

プロセッサ上で実際に実行するタスクを切換える場合に
は、現在実行中のタスクに関する状態情報をタスク制御
ブロックに退避したうえで(以下己れをロールアウトと
称す)次に実行すべきタスクの状態情報を対応するタス
ク制御ブロックから読出し、プロセッサに書き戻す(こ
れを以下ロールインと称す)。従来にこのタスク切換え
は1機械語命令と機械語命令との間で行われていた。
When switching the task to be actually executed on the processor, the state information regarding the currently executing task is saved to the task control block (hereinafter referred to as rollout), and the state information of the task to be executed next is saved. is read from the corresponding task control block and written back to the processor (hereinafter referred to as roll-in). Conventionally, this task switching was performed between one machine language instruction and another machine language instruction.

しかしながら、情報処理装置のプロセッサの大型化が進
み、高速化のためパイプライン処!等の高度の制御を取
入れたプロセッサにおいてに、タスクの切換えを行うこ
とにエリ実行中のパイプラインが中断され、処理効率が
大幅に低下するという問題点があった。
However, as processors in information processing devices become larger, pipeline processing is required to increase speed. In processors that incorporate advanced control, such as the above, there is a problem in that switching tasks interrupts the pipeline during execution, resulting in a significant drop in processing efficiency.

さらvc1ベクトル処理を高速に行うベクトルプロセッ
サにおいては、内部レジスタとしてベクトル処理専用の
大量のレジスタ(通常ベクトルレジスタと呼ばれる)を
もっており、これを使用している場合VCl−jタスク
切換えに際しては、その内容も、内部状態としてロール
アウト、ロールインする必要があり、タスク切換えのオ
ーバヘッドが極めて大きくなるという問題がある。
Furthermore, a vector processor that performs vc1 vector processing at high speed has a large number of registers dedicated to vector processing (usually called vector registers) as internal registers, and when these are used, their contents are However, it is necessary to roll out and roll in the internal state, and there is a problem in that the overhead of task switching becomes extremely large.

(発明の目的) 本発明の目的に前述の従来のタスク切換えのオーバヘッ
ドを削減するために1機械語命令プログラムの実行1;
際して、i1*プログラムのなかで内部状態が少くタス
ク切換えが発生しても比較的小さなオーバヘッドでタス
ク切換えが可能な箇所に、特別な機械語命令を埋めこみ
、この命令が検出されたことを契機に、必要なタスク切
換えを行ないタスク切換えのオーバヘッドを削減できる
情報処理装置を提供することにある。
(Object of the Invention) The object of the present invention is to execute one machine language instruction program in order to reduce the overhead of the conventional task switching described above;
In this case, a special machine language instruction is embedded in a part of the i1* program where the internal state is small and task switching can be performed with relatively small overhead even if a task switching occurs, and the detection of this instruction is detected. It is an object of the present invention to provide an information processing device that can take advantage of this opportunity to perform necessary task switching and reduce task switching overhead.

(発明の構ff) 本発明の装[1に、タスク切換えのオーバヘッドが少な
いことを示す特定機械語命令を設け、前記特定機械語命
令を解読し第1の信号を発生する命令デコード手段と、
タスク切換要求を一時記憶する記憶手段と、前記第1の
信号の供給に応答して前記記憶手段を検査しタスク切換
要求が記憶ばれてrるときにはタスク切換処理を起動す
る起動信号を発生するタスク切換起動手段とを含んで構
成される。
(Structure of the Invention) The apparatus of the present invention [1 is provided with a specific machine language instruction indicating that the overhead of task switching is small, and an instruction decoding means for decoding the specific machine language instruction and generating a first signal;
storage means for temporarily storing a task switching request; and a task for checking the storage means in response to the supply of the first signal and generating an activation signal for starting task switching processing when the task switching request is stored. and switching activation means.

(実施例) 次に本発明の賽施f+1について図面を参照して説明す
る。
(Example) Next, the sacrifice f+1 of the present invention will be explained with reference to the drawings.

iE1図は本発明の一笑路側の要部を示すブロック図で
あり、特定命令を解読するデコード回路lと、タスク切
換要求を一時記憶するタスク切換要求保持回路2と、タ
スクの切換を起動するタスク切換起動回路3とを含んで
いる。
Figure iE1 is a block diagram showing the main parts of the side of the present invention, including a decoding circuit 1 for decoding a specific command, a task switching request holding circuit 2 for temporarily storing a task switching request, and a task for starting task switching. It includes a switching starting circuit 3.

上記の特定命令(以下これをタスク切換契機指定命令と
称す)は第3図にそのフォーマットが示されているよう
に、1バイトの命令コード部のみよりなる機械語命令で
あり命令コードとしてこれがタスク切換契機指定命令で
あることを示す特定の値をもっている。しかしてこの命
令はプログラムの中でタスク切換のオーバヘッドの少い
個所を示すために使用されるものとす為。従ってこの命
令のあるプログラムの個所はタスク切換の契機となる個
所を示すことになる。
As the format of the above specific instruction (hereinafter referred to as the task switching trigger specification instruction) is shown in Figure 3, it is a machine language instruction consisting of only a 1-byte instruction code section, and this is the instruction code for the task switching trigger specification instruction. It has a specific value indicating that it is a switching trigger designation command. However, this instruction is assumed to be used to indicate a point in the program where the overhead of task switching is low. Therefore, the location in the program where this instruction is located indicates the location that triggers task switching.

タスク切換要求保持回路2に入力されるタスク切換要求
は現在実行中のタスクと比較し最優先に切換を必要とす
るタスクの切換要求が到来するものとする。
It is assumed that the task switching request inputted to the task switching request holding circuit 2 is compared with the task currently being executed, and a switching request for a task that requires switching with the highest priority arrives.

@2図は本実施例の動作を示す流れ図である。@2 Figure is a flowchart showing the operation of this embodiment.

第1図と第2図とにより本実施例の動作について説明す
る。
The operation of this embodiment will be explained with reference to FIGS. 1 and 2.

実行される機械語命令が読出されデコード回路1に供給
される。供給される機械語命令がタスク切換契機指定命
令であるときにはデコード回路1はこれを解読し一致信
号をタスク切換起動回路3に供給する。タスク切換起動
回路3に一致信号の供給に応答してタスク切換要求保持
回路2にタスク切換要求が保持されているかどうかを調
ベタスク切換要求が保持されているときにはタスク切換
起動回路3はタスク切換起動信号を発生しこれによりタ
スク切換処理を開始せしめる。タスク切換ル 要求保持回路2タスク切換要求が保持されていないとき
にはタスク切換起動信号は発せられずプログラムの実行
にタスク切換契機指定命令の次の命令に移る。
A machine language instruction to be executed is read out and supplied to the decoding circuit 1. When the supplied machine language command is a task switching trigger designation command, the decoding circuit 1 decodes it and supplies a matching signal to the task switching starting circuit 3. In response to the supply of the matching signal to the task switching starting circuit 3, it is checked whether the task switching request is held in the task switching request holding circuit 2. If the task switching request is being held, the task switching starting circuit 3 starts the task switching. A signal is generated to start the task switching process. Task switching request holding circuit 2 When the task switching request is not held, the task switching start signal is not issued and the program execution moves to the next command after the task switching trigger designation command.

以上、本発明の実施例を説嬰したが5本実施例の説明で
明らかなLうに、本発明の主旨は、タスク切換えのオー
バヘッドが少いことを示す特別の機械語命令を設け、こ
の命令の実行に際してはタスク切換えに関する要求があ
る場合には、タスク切換えに関する処理をこの命令を契
機として開始し、要求がない場合には無効命令と等価の
機能を果すようにすることにエリ、タスク切換えのオー
バヘッドが少い時点でのみタスクの切換えが発生するよ
うにし、これにより情報処理装置の処理能力を向上させ
ること?可能にすることにある。
The embodiments of the present invention have been described above, but as is clear from the explanation of the five embodiments, the gist of the present invention is to provide a special machine language instruction that shows that the overhead of task switching is small, and to use this instruction. When executing this command, if there is a request for task switching, processing related to task switching will be started using this command as a trigger, and if there is no request, the task switching will be performed so that the function equivalent to an invalid command is performed. Is it possible to improve the processing capacity of information processing equipment by ensuring that task switching occurs only when there is little overhead? It's about making it possible.

従って本発明の主旨に背かぬ限り、いくつかの実現方法
があることに明らかであろう。
Therefore, it is clear that there are several ways to implement the invention as long as they do not go against the spirit of the invention.

前述の本発明の主旨とは直接の関係がなく、かつ従来知
られている方法で実現できる理由に工りと 上記の実施例ではタスク切換えの状態管れれに基〈タス
クに関する処理についてに詳細の説明を省いである。即
ち、前者は外部割込み、インターバルタイマ割込み等の
割込みを受は付け、その内容を解析し、この割込みによ
り新たに実行可能になったタスクがある場合には、この
タスクの状態を更新するとともにこのタスクと現在実行
中のタスクとを比較し、タスクの切換えを行う必要があ
るかどうかを決定し、必要がある場合ににこの要求を保
持する機能をもち、(タスク切換要求保持回路2はこの
要求を保持する)後者は前者の決定にもとづき、実際の
タスクの切換えを制御する部分である。
The reason for this is that it is not directly related to the above-mentioned gist of the present invention, and that it can be realized by a conventionally known method. I'll omit the explanation. That is, the former accepts interrupts such as external interrupts and interval timer interrupts, analyzes their contents, and if there is a task that has become newly executable due to this interrupt, it updates the state of this task and updates this task. It has the function of comparing the task with the currently executing task, determining whether it is necessary to switch the task, and holding this request if necessary (the task switching request holding circuit 2 The latter (which holds the request) is the part that controls actual task switching based on the former's decision.

本実施例において、これらはすべて専用のノ\−ドウ1
アにLり実現されていても工いし、一部あるいに全部の
処理が情報処理装置内の既存のハードv′7τγを用い
て実現されても工〈、これらの各場合vc工って本発明
の具体的な実現方法が異ることに明らかであろう。
In this embodiment, these are all dedicated nodes.
It is possible to implement the process even if it is realized in A, or even if some or all of the processing is realized using the existing hardware v′7τγ in the information processing device. In each of these cases, the process is It will be obvious that the specific implementation methods of the present invention are different.

たとえば専用のハードウェアで実現されている場合には
プロセッサ部でのタスクの実行と並行して、割込み等が
受付けられタスクの管理上行い、現在実行中のタスクと
新たに実行可能になりtタスクとの間で切換えを行う必
要があるかどうかを決定し、必要がある場合にはこの要
求を保持する。
For example, if it is implemented with dedicated hardware, interrupts, etc. are accepted in parallel with the execution of tasks in the processor section, and are performed for task management, and the currently executing task and new tasks are made executable. determine whether it is necessary to switch between the two and maintain this request if necessary.

タスクの実行において、タスク切換契機指定命令の実行
が検出されると、先の保持されている要求を調べ、これ
がある場合にはタスク切換え手段を起動する。専用ハー
ドウェア上で動くタスク切換え手段に、現在実行中のタ
スクをロールアウトし、新たなタスクをロールインした
後プロセッサ部での処理を再開する。これにより新たな
タスクが起動される。ロールアウトされたタスクは次に
ロールインされた時点では、タスク切換契機指定命令の
次の命令から実行を再開することになる。
When execution of a task switching trigger designation command is detected in the execution of a task, the previously held request is checked, and if there is one, the task switching means is activated. A task currently being executed is rolled out to a task switching means running on dedicated hardware, a new task is rolled in, and processing in the processor section is resumed. This starts a new task. When the rolled-out task is next rolled in, execution will resume from the command following the task switching trigger designation command.

また、割込み要求等だけをタスク切換えに関する要求と
して取扱い、タスクの状態変更、タスク切換えの要否等
の判定は、本発明による特別の命令が実行された時点で
行うようにすることも可能であろう。
Furthermore, it is also possible to treat only interrupt requests and the like as requests related to task switching, and to determine whether or not task status changes and task switching are necessary at the time when a special instruction according to the present invention is executed. Dew.

(発明の効果) 本発明によるタスク切換契機指定命令をたとえばベクト
ルプロセッサ上で動くプログラムにおいて、これまで使
用していたベクトルレジスタを開放した箇所に埋込むこ
とにより、ベクトルレジスタの退避を不要にすることが
可能となり、タスク切換えを高速に行うことが可能とな
り、tW報処理装置の処理能力を向上できるという効果
がある。
(Effects of the Invention) By embedding the task switching trigger designation instruction according to the present invention in a program running on a vector processor, for example, in a place where the previously used vector register has been released, it is possible to eliminate the need to save the vector register. This makes it possible to perform task switching at high speed, and has the effect of improving the processing capacity of the TW information processing device.

【図面の簡単な説明】 jig1図は本発明の一実施例の要部を示すブロック図
、第2図は第1図の動作を示す流れ図お工び第3図は本
発明に使用する命令のフォーマット図である。 1・・・・・・デコード回路、2・・・・・・タスク切
換要求保持回路、3・・・・・・タスク切換起動回路。
[Brief Description of the Drawings] Figure 1 is a block diagram showing the main parts of an embodiment of the present invention, Figure 2 is a flowchart showing the operation of Figure 1, and Figure 3 is a flow diagram of the instructions used in the present invention. It is a format diagram. 1... Decoding circuit, 2... Task switching request holding circuit, 3... Task switching starting circuit.

Claims (1)

【特許請求の範囲】 タスク切換えのオーバヘッドが少ないことを示す特定機
械語命令を設け、 前記特定機械語命令を解読し第1の信号を発生する命令
デコード手段と、 タスク切換要求を一時記憶する記憶手段と、前記第1の
信号の供給に応答して前記記憶手段を検出しタスク切換
要求が記憶されているときにはタスク切換処理を起動す
る起動信号を発生するタスク切換起動手段とを含むこと
を特徴とする情報処理装置。
[Scope of Claims] A specific machine language instruction indicating that the overhead of task switching is small is provided, an instruction decoding means for decoding the specific machine language instruction and generating a first signal, and a memory for temporarily storing the task switching request. and task switching starting means for detecting the storage means in response to the supply of the first signal and generating a starting signal for starting task switching processing when a task switching request is stored. Information processing equipment.
JP7483885A 1985-04-09 1985-04-09 Information processor Pending JPS61233838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7483885A JPS61233838A (en) 1985-04-09 1985-04-09 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7483885A JPS61233838A (en) 1985-04-09 1985-04-09 Information processor

Publications (1)

Publication Number Publication Date
JPS61233838A true JPS61233838A (en) 1986-10-18

Family

ID=13558873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7483885A Pending JPS61233838A (en) 1985-04-09 1985-04-09 Information processor

Country Status (1)

Country Link
JP (1) JPS61233838A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01140341A (en) * 1987-11-27 1989-06-01 Mitsubishi Electric Corp Programmable controller
JP2011028440A (en) * 2009-07-23 2011-02-10 Nec Corp Multithread processor and computer program

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144242A (en) * 1976-05-27 1977-12-01 Mitsubishi Electric Corp Multi-task control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144242A (en) * 1976-05-27 1977-12-01 Mitsubishi Electric Corp Multi-task control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01140341A (en) * 1987-11-27 1989-06-01 Mitsubishi Electric Corp Programmable controller
JP2011028440A (en) * 2009-07-23 2011-02-10 Nec Corp Multithread processor and computer program

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