JPS60198646A - Error producing system of control storage - Google Patents

Abstract

PURPOSE:To test errors of all CS (control storage) addresses by producing an error at an optional area of a microprogram forming an instruction with no dependence on the data to be processed. CONSTITUTION:The address information which is executed earlier by an amount equivalent to a prescribed number of addresses than a CS address where an error should be produced after the operation of a data processor is stopped is set to a CS address pointer 6. While the prescribed count number is set to a CS counter 8. Then the data processor compares the CS address with the pointer 6 through a comparator 7. When the coincidence is obtained from this comparison, the comparator 7 stores the coincident state by an internal latch and performs no address comparison any more. The comparator 7 indicates a subtracting action of the counter 8. Then the data value given from a register 4 is inverted to produce an error when the result of subtraction is equal to ''0''. Thus an error test is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to a microprogram-controlled data processing device, and particularly to a control storage (C3)
It is concerned with causing an error in a microprogram stored in a computer.

(b) Conventional technology and problems Conventionally, when a microprogram error occurs,
The microprogram to be loaded into the C3 of the data processing device was destroyed and written in advance, and an error occurred when it was read out. However, with microprogram-controlled data processing devices, the address of the microprogram depends on the type of data to be processed. This had the disadvantage that it was not guaranteed that a microprogram that had been corrupted in advance would actually be used and cause an error.

(c) Purpose of the Invention The purpose of the present invention is to
The purpose of this invention is to provide a device that generates an error.

- (d) Structure of the Invention In order to achieve the above object, the present invention provides a control storage address at which an error should occur in a data processing device that has a control storage that stores a microprogram and operates under the control of the microprogram. address pointer means for holding address information for an address point to be executed a predetermined number of addresses earlier; counter means for initializing a predetermined count value in order to perform a counting operation for the predetermined addresses; an address comparing means for comparing the address information held in the pointer means with a control storage address to be actually executed; and a counting operation for the value of the counter means from the time when an address match is detected by the address comparing means. and data inversion means for inverting data read from the control storage when the value of the counter means reaches a predetermined value by the counting means, It is characterized by being configured to cause an error to occur.

(E) Examples of the invention The present invention will be explained below with reference to the drawings.

The figure is a block diagram of main parts of a data processing device according to an embodiment of the present invention, and in the figure, 1 is an instruction decoder.

2 is a CS address register, 3 is a C3, 4 is a CS read register, 5 is a CS data inversion circuit, 6 is a CS address pointer, 7 is a CS address comparison circuit, 8 is a CS counter, and 9 is a subtraction circuit.

The operation of the embodiment is as follows.

First, after stopping the data processing device or by using a diagnostic instruction, the address information about the address point that is executed a predetermined number of addresses ahead of the control storage (C3) address that should cause the error is transferred to the CS address. At the same time, a predetermined count value for counting a predetermined address is set in the CS counter 8.

Next, the data processing device is operated. In the data processing device, an instruction decoder 1 analyzes an instruction read from a main storage device (not shown), etc., and stores a CS address in a CS address register 2. At the same time, this CS address and the contents of the CS address pointer 6 are compared in a CS address comparison circuit 7. As a result of the comparison, if they do not match, the instruction decoder 1 performs an instruction analysis operation, sets the CS address in the CS address register 2, and compares the CS address with the contents of the CS address pointer 6, which are repeated. At this time, needless to say, the microprogram instructions are sequentially read out to the C8 read register 4 starting from C33, and the required operations are executed.

Next, at a certain point, when the CS address from the instruction decoder 1 and the contents of the CS address pointer 6 match, the C
The S address comparison circuit 7 stores the matching state using an internal latch (not shown) and does not perform address comparison thereafter. After detecting a CS address match, the CS address comparison circuit 7 instructs the subtraction circuit 9 to subtract the contents of the CS counter 8.

As a result, the subtraction circuit 9 performs a 11 subtraction operation on the contents of the CS counter 8 every cycle of C33. If the subtraction result is not "0", the instruction decoder 1 performs an instruction analysis operation.

The operation of setting the CS address in the CS address register 2 and the operation of taking out data from C33 are repeated.

As a result of proceeding with the subtraction operation in this way, when the subtraction result becomes "0", the subtraction circuit 9 sends a data inversion instruction signal to the CS data inversion circuit 5, and the data is read out from the C8 read register 4. Inverts the value of data. After this, the operation of the subtraction circuit 9 stops.

As a result, an error will occur in the data read from C8, making it possible to perform various error tests.

(F) Effects of the Invention According to the present invention, it is possible to generate an error in any part of a microprogram that constitutes an instruction, independent of the data to be processed, and to test for errors in all CS addresses. becomes possible.

[Brief explanation of drawings]

The figure is a block diagram of main parts of a data processing device according to an embodiment of the present invention, and in the figure, 1 is an instruction decoder. 2 is a CS address register, 3 is a C3, 4 is a CS read register, 5 is a CS data inversion circuit, 6 is a CS address pointer, 7 is a CS address comparison circuit, 8 is a CS counter, and 9 is a subtraction circuit.

Claims (1)

[Claims] In a data processing device that has a control storage that stores a microprogram and operates under microprogram control, it holds address information about an address point that is executed a predetermined number of addresses before the control storage address that should cause an error. a counter means to which a predetermined count value is initially set in order to perform a counting operation for the predetermined addresses; and address information held in the address pointer means and control storage to be currently executed. address comparison means for comparing the address with the address; means for performing a counting operation on the value of the counter means from the time point when address matching is detected by the address comparison means; 9. An error generation method for a control storage, comprising: data inversion means for inverting the data read from the control storage when the error occurs, and generating an error in the data read from the control storage. .