JPH02230336A - Information processor - Google Patents

Abstract

PURPOSE:To accurately retrieve the existence address of a target write instruction in a short time by setting a destroyed address from an external panel when the address is destroyed by means of a program bug. CONSTITUTION:When the address is destroyed by the program bug, the destroyed address is stored in a register 30 when the address where the instruction being the cause exists is retrieved. When a mode which has been set in a maintenance mode setting part 10 is a debug mode, the content of the register 30 comes to the input of a comparison circuit 50 by an AND circuit 40. On the other hand, the content of a write address storage register 70 storing the write address comes to be the input of the comparison circuit 50 when an instruction which is accompanied by a write action is executed. When the compared result coincide in the comparison circuit 50, address coincident signals 55 and 56 are turned on and a debug interruption occurs in a debug interruption generation circuit 95. Thus, the instruction address where the instruction exists is accurately and easily seized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an information processing device having a program debugging function. Conventionally, in order to search for the address where the write instruction that caused the destruction of the destroyed address exists, there is a method of searching the program list for a write instruction that makes the destroyed address the overland address. There are also other methods as follows. Actually, the program is run in small step groups of about 10 to 100 steps, and after each run, the destroyed address is checked and if it is not destroyed, the program moves to the next small step group and the same operations as above are repeated. Another method is to gradually narrow down the address range where the write instruction that caused the destruction exists, and finally obtain the address where the write instruction that caused the destruction exists. Among the conventional methods described above, in the former method, the program list is searched for the write instruction that caused the destruction to the destroyed address by checking for write instructions that have the destroyed address as the operand address. However, due to human carelessness, it may be overlooked and not discovered. Additionally, some of the generated operand addresses are determined after the information processing device is running (address modification by registers means that the value in the register becomes part of the operand address), so it can only be determined visually on the list. There is a limit. On the other hand, in the latter method of actually running the program little by little and searching for the target instruction, a group of small steps of about 10 to 100 steps are executed and the address to be destroyed is checked each time, so for example, Even in a program with about 10,000 steps, the above-mentioned operations have to be repeated 100 times, so debugging takes a lot of time.
An object of the present invention is to provide an information processing device that can accurately and quickly search for an address where a target write command exists. An information processing apparatus according to the present invention includes a storage means for storing a write address of an instruction executing a write operation, and a debug interrupt when a preset address to be destroyed matches the write address. and means for outputting the address where the instruction that executed the write operation exists when the two addresses match. Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, reference numeral 1 denotes an external panel, which has a maintenance mode setting section 10 and a destruction address setting section 20. Reference numeral 30 is a register for storing the address to be destroyed that has been set in advance in the address to be destroyed section 20. Reference numeral 40 denotes an AND circuit that handles the output of the maintenance mode setting section 10 and the contents of the register 30 by two people, and when the mode set in the maintenance mode setting section 10 is the debug mode, it is turned on and the contents of the register 30 are input. Derive. 50 is a comparison circuit that compares the contents of the register 30 (destroyed address), which is the output of the AND circuit 40, and the contents of the write address storage register 70. When an instruction involving a write operation is executed, the write address at that time is temporarily stored in this register 70. If the addresses of both registers 30 and 70 show a match as a result of comparison #150, both address match signal lines 55 and 56 are turned on. 9
5 is a debug interrupt circuit for receiving this address match signal line 56 and turning on a debug interrupt signal line 98. Reference numeral 60 denotes a write operation instruction address storage register that stores the address at which an instruction involving a write operation exists when the instruction is executed. Reference numeral 80 denotes an AND circuit that combines the contents of this register 60 and the address match signal I155 of the comparator circuit 50, and the output of this AND circuit 80 is introduced into the destructive operation instruction address storage register 90. In such a configuration, if a certain address is destroyed due to a bug in the program, when searching for the address where the instruction that caused the problem exists, the destroyed address is preset in the setting section 2.
It is set by 0 and stored in the register 30. When the mode set in the maintenance mode setting section 10 is debug mode, the contents of this register 30 are input to the comparator circuit 50 by the unF circuit 40. On the other hand, when an instruction involving a write operation is executed, the contents of the write address storage register 70 that stores the write address at that time become input to the comparator circuit 50. In this comparison circuit 50,
If the comparison results match, address match signal lines 55 and 56, which are the outputs of the comparison circuit 50, are both turned on. When the address match signal line 56 is on, the debug interrupt generation circuit 95
Turn on the debug interrupt signal line 98 to generate a debug interrupt. Furthermore, when an instruction involving a write operation is executed, the output of the write operation instruction address storage register 60 that stores the address where the instruction exists is input to the AND circuit 80.
On the other hand, if the comparison results match in the comparison circuit F#I50, the output address match signal line 55 is turned on.
This becomes the input to the AND circuit 80. When the address match signal line 55 is on, the contents of the write operation instruction address storage register 60 become the output of the AND circuit 80, and the address where the instruction that has been executed with the write operation exists is the destructive operation instruction address storage. It will be output to register 90 and stored. As described above, in the information processing apparatus according to the present invention, the address set by the address to be destroyed setting unit 20 and the write address storage register 7
When the address 0 matches, a debugging interrupt can be generated, and a debugging program can be started in response to this interrupt. Furthermore, it is also possible to store the existing address of the instruction that executed the destructive operation in the destructive operation instruction address storage register 90. According to the present invention, when a certain address is destroyed due to a program bug, by setting the destroyed address from the external panel, the instruction address where the instruction that caused the destruction exists can be accurately and This has the advantage of being easy to capture, and at the same time allowing a debug program to be started using a debug interrupt.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. Explanation of symbols of main parts 20...Destroyed address setting section 30...Destroyed address storage register 50...
... Comparison circuit 60 ... Write operation command address storage register 70
...Write address storage register 95...
Debug interrupt generation circuit

Claims (1)

[Claims] (1) Storage means for storing the write address of the instruction executing the write operation; means for generating a debug interrupt when a preset address to be destroyed matches the write address; an information processing apparatus comprising: means for outputting an address where an instruction that executed the write operation exists when the instructions match.