JP3213792B2 - Logic simulation verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic for verifying a logic simulator by comparing the result of executing a logic verification program with a logic simulator and the result of executing the logic verification program with a single instruction sequential execution type instruction simulator. The present invention relates to a simulation verification method.

[0002]

2. Description of the Related Art As a technique for supporting high-performance instruction processing, instruction execution is divided into a plurality of processing steps (stages), and each device (control unit) executes a specific stage every one machine cycle. A pipeline processing method for processing is adopted. This pipeline processing, also called the advanced control function, is realized by complex and large-scale logic.
The degree of precedence control is very deep. for that reason,
At the time of instruction fetch and data access, preemption of the RAM (cache, TLB) to be accessed works by preceding control, and the contents of the RAM are frequently updated. In the conventional result checking method, since the update time / unit of the RAM differs for each model, a verification program having a result comparison function unique to each model is executed by the logic to be verified, and the execution result is compared with the result comparison function of the verification program itself. Has confirmed. In the batch compare method of the execution result of the single-instruction sequential execution type instruction simulator and the execution result of the logic to be verified, the cause of the mismatch is that the single-instruction sequential execution type instruction simulator uses one instruction at a time. Therefore, it is realized by analyzing whether or not there is a mismatch by manual intervention. As a related conventional technique of this kind, for example, a technique described in Japanese Patent Application Laid-Open No. 5-67966 is known.

[0003]

In the prior art, the result comparison processing routine compares the execution result (expected value) of the single instruction successive execution type instruction simulator and the execution result of the logic to be verified, and collectively compares the result. If there is a mismatch in the contents, the cause of the mismatch will be manually investigated based on information such as an error message. However, it is necessary to examine the instruction trace, the logic execution trace, and the like to determine whether the mismatch is caused by the prefetching of the RAM by the preceding control of the logic to be verified or the logic to be verified is defective. is there. Such inconsistency frequently occurs even in a verification program (single instruction test or the like) that does not target the preceding control as a verification target, and it is a situation in which batch comparison of the RAM must be suppressed. For this reason, only inconsistencies that occur in a verification program that targets the update control of the RAM are investigated by manual intervention. In this investigation, since manual intervention is required, the contents of verification (test instruction sequence, target RAM state, etc.) and the logic to be verified must be grasped, and analysis is difficult.
Further, only a part of these verification programs cannot guarantee whether or not the update control of the RAM is appropriate, which is one of the factors that makes it difficult to extract a logic defect. An object of the present invention is to solve the above-mentioned problem and to use a batch conveyor system in which the occurrence of a compare mismatch of a RAM only at the time of a true mismatch (at the time of detecting a failure of a logic to be verified) in all the verification programs. And a highly accurate verification method.

[0004]

In order to achieve the above object, the present invention provides a logic simulator for executing a logic verification program, a single instruction sequential execution type instruction simulator, and an execution result of the logic simulator. A result value file, an expected value file for storing execution results of the single instruction sequential execution type instruction simulator, a batch comparing means for comparing the storage contents of the result value file with the storage contents of the expected value file, A logic simulation verification method including a batch compare result file that stores the output of the instruction, prefetching instructions that are executed by the logic simulator but are not executed by the single instruction sequential execution type instruction simulator, prefetching data, and Includes processing for updating the contents of the cache and TLB such as RAM contention A pre-processing condition file storing the contents of the processing corresponding to the instruction address of the instruction is connected to the single instruction sequential execution type instruction simulator, and the single instruction sequential execution type instruction simulator Search the preceding processing condition file by address,
When the contents of the corresponding processing are retrieved, the RAM updating including the prefetched instruction address, the target address at the time of data access, the initial value of the data cache column to be updated, etc. is performed based on the contents of the processing. Generate the data, R
It is registered in the AM update data file. Further, if the result of the comparison by the batch compare means indicates a mismatch, a warning is displayed when the mismatch is registered in the RAM update data file, and an error is displayed when the content is not registered. I have. Further, the logic simulator is an actual data processing device.

[0005]

According to the above-mentioned means, it is possible to automatically check the validity of updating the contents of the RAM, which has conventionally been confirmed as a result of manual intervention. As a result, it is possible to check the test results in a shorter time than before, and it is possible to improve the verification accuracy by applying to the running of all test programs.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a process for checking the validity of updating the contents of a RAM and performing a batch comparison of test results according to an embodiment of the present invention. (1) The logic simulator (processor operation simulator under development describing an intermediate language at the wiring level) 101 executes the verification program 100 and collects the execution result in the result value file 104.

(2) The single instruction successive execution type instruction simulator 102 executes a verification program and collects the execution result in an expected value file 105. For example, when the logic simulator 101 executes a Branch instruction, as shown in FIG. 2, a process of prefetching the next eight non-executable instructions following the Branch instruction into the instruction cache has already been performed. However, since the single-instruction successive execution type instruction simulator 102 reads and executes one instruction at a time, it does not perform prefetching of instructions to the instruction cache. Therefore, the pre-processing condition file 103 includes the Br executed by the single instruction successive execution type instruction simulator 102.
The instruction address of the “anch” instruction and the content “a” of prefetching to be executed by the logic simulator 101 corresponding to the instruction address are stored in advance, and the single instruction successive execution type instruction simulator 102 The preceding processing condition file 103 is searched. Processing content a: Branch Code Cache = +
8 Single instruction The instruction executed by the successive execution type instruction simulator 102 is a Branch instruction, and when the instruction address matches the instruction address stored in the pre-processing condition file 103, the instruction is read from the pre-processing condition file 103. The processing content a corresponding to the address is read. When the processing content a is read, the single instruction successive execution type instruction simulator 102 includes an instruction address next to the address of the Branch instruction.
Update data Code CacheCLM = 1, EV = 1, ADR =
100, DATA = 012F is generated and registered in the RAM update data file 106. The above processing includes prefetching of instructions by the logic simulator, prefetching of data, and RA in the same column.
The processing for updating the contents of the cache and TLB such as M contention is similarly performed.

(3) The result value file 104 and the expected value file 105 are subjected to a batch compare process 107.

At this time, if the contents of the RAM do not match, R
By referring to the AM update data file, a warning display is output to the result file 108 of the batch compare if the condition is registered in the target RAM, and an error display is output to the non-target RAM.

FIG. 3 is a diagram showing the pre-processing condition file reference and R
This is a flowchart showing an AM update data file registration process. Hereinafter, each step of FIG. 3 will be described in detail. When an expected value is generated in the single instruction successive execution type instruction simulator 102, an instruction execution sequence is collected as an instruction execution trace. At this time, if the instruction address becomes non-contiguous due to the occurrence of a branch or interrupt, it is assumed that the precedent control will work and prefetching of the instruction cache will be performed. May have been included in The single instruction successive execution type instruction simulator 102 searches and checks the preceding processing condition file 103 according to the instruction address to be executed (201). If a discontinuous instruction address is generated, the RAM update data including the instruction address next to the instruction address that caused the discontinuity is registered in the RAM update data file (202). Also, assuming that the execution result of the instruction executed last by the data access execution does not remain in the cache, the instruction before and after the prefetch access to the data cache (prefetch operation to the data cache) and the like are used. When an instruction whose execution order is not guaranteed is executed, the preceding processing condition file 103 is searched and checked according to the instruction address to be executed (203). as a result,
If there is a match, the RAM update including the target address at the time of data access is registered in the RAM update data file (204). Also, assuming that the data cache to be updated conflicts with the data cache to be updated due to the data access execution and the data access execution is invalidated, the data access execution is performed for another continuous data access. When updating the same cache column as the execution, the preceding processing condition file 103 is searched and checked by the instruction address to be executed (205). As a result, if there is a match, the RAM update data including the initial value of the update target data cache column is
It is registered in the AM update data file (206).

FIG. 4 is a flowchart showing a RAM update data file reference process. Hereinafter, each step of FIG. 4 will be described in detail. The result value file 104 created by the logic simulator 101 and the expected value file 10 created by the single instruction successive execution type instruction simulator 102
5 are compared (301), and if they match, it is determined to be normal, and the batch comparison result is displayed (306). In the case of a mismatch, if the content of the mismatch is registered in the RAM update data file (302), a warning is displayed (304), and no error is treated in the comparison result. Registered data
Inconsistencies other than the data, an error is displayed as either an expected value defect (a defect on the single instruction successive execution type instruction simulator side) or a result value defect (a defect on the verified logic side) (303). ). In this case, the RAM update data 305 is attached as additional information and used for failure analysis.

The above processing contributes to shortening of the failure analysis time due to occurrence of a mismatch in the comparison result, and improvement of the verification accuracy by being applied to all verification programs.
Although the embodiment of the present invention has been described above, this batch compare method is applicable to an actual data processing device in addition to the logic simulation.

[0013]

As described above, according to the present invention, it is possible to efficiently and accurately execute a logic verification on a logic simulator or a real data processing device to be verified. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a process of checking the validity of updating the contents of a RAM and performing a batch comparison of test results.

FIG. 2 is a diagram illustrating a prefetching state of an instruction by a logic simulator when a Branch instruction is executed.

FIG. 3 shows RA in a single instruction sequential execution type instruction simulator.
FIG. 9 is a flowchart showing a process of generating and registering an M update data file.

FIG. 4 shows batch comparison processing and R in the result comparison module.
FIG. 14 is a flowchart showing a method of referring to a RAM update data file when the results of AM comparison do not match, and a flowchart of the validity check process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 verification program file 101 logic simulator 102 single instruction successive execution type instruction simulator 103 pre-processing condition file 104 result value file 105 expected value file 106 RAM update data file 107 compare process 108 batch compare result file

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-225276 (JP, A) JP-A-4-190457 (JP, A) Norio Utsumi, four others, “Translati for high-performance microprocessors Performance Evaluation of on-Lookside-Buffer ", Proc. of the National Convention of IPSJ, IPSJ, 1992, Vol. 45, no. 6, p. 119-120 Takao Yamamoto, et al., "Performance Analysis of Microprocessor Configuration by Software Simulator", IEICE Technical Report, IEICE, 1992, ICD92-76, p. 17-24 (inside the agency Literature number: CCNT199900533003) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 G06F 11/25 JICST file (JOIS)

Claims (2)

(57) [Claims] 1. A logic simulator for executing a logic verification program, a single instruction sequential execution type instruction simulator, a result value file for storing an execution result of the logic simulator, and execution of the single instruction sequential execution type simulator A logic simulation verification method comprising an expected value file for storing results, a batch compare means for comparing the stored contents of the result value file with the stored contents of the expected value file, and a batch compare result file for storing the output of the means. A cache including instruction prefetching , data prefetching , or RAM contention processing in the same column, which is executed by the logic simulator but not executed by the single instruction sequential execution type instruction simulator.
The preceding processing condition file storing the content of the processing corresponding to the instruction address of the instruction processing accompanying the contents of the updated provided, said single instruction executed sequentially type instruction simulator, the instruction address per executing instructions By searching the preceding processing condition file, and when the content of the corresponding process is retrieved, based on the content of the process, the prefetched instruction address,
Or RA including a target address at the time of data access or an initial value of a data cache column to be updated.
M update data is generated and registered in the RAM update data file.
Recorded, and as a result of comparison by the batch compare means,
If not, the content of the mismatch is stored in the RAM update data file.
When registered, a warning is displayed and the registered
A logic simulation verification method characterized by displaying an error when there is no error . 2. The logic simulation verification method according to claim 1, wherein said logic simulator is a real data processing device .