JPH08263544A - Logic simulation verification system - Google Patents

Abstract

PURPOSE: To provide a batch comparison system which detects a comparison discrepancy of a RAM only when a real discrepancy is generated (when a defect in logic to be verified is detected). CONSTITUTION: A verifying program 100 is executed by a logic simulator 101 and an instruction simulator 102 and results are stored in a file 104 and a file 105 respectively, and the contents of the files are compared 107 at a time and the result is stored in a file 108. In the file 103, instructions which are executed by the logic simulator 101, but not executed by the instruction simulator 102 are cached by instruction prefetching, etc., the contents of a process corresponding to an instruct address accompanied by an updating process for the contents of a TBL are stored, and the instruction simulator 102 retrieves a condition file 103 with instruction addresses each time an instruction is executed, generates RAM update data including the prefetched instruction address, etc., on the basis of the contents of the corresponding process when the contents are taken out, and registers them in a file 106. When a discrepancy is detected as a result of the comparison, an alarm is displayed on condition that the discrepant contents are registered in the file 106, but an error display is made when not.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a logic for verifying a logic simulator by comparing the result of executing a logic verification program with a logic simulator and the result of executing the logic verification program with a single instruction sequential execution type instruction simulator. The present invention relates to a simulation verification method.

[0002]

2. Description of the Related Art As a technique for improving the performance of instruction processing, instruction execution is decomposed into a plurality of processing steps (stages), and each device (control unit) executes a specific stage every machine cycle. A pipeline processing method for processing is adopted. The pipeline processing, which is also called the advanced control function, is realized by complex and large-scale logic.
The degree of advance control is very deep. for that reason,
At the time of instruction fetch or data access, the RAM (cache, TLB) to be accessed is prefetched by the advance control, and the contents of the RAM are updated frequently. In the conventional result confirmation method, since the RAM update timing / unit is different for each model, a verification program having a result comparison function unique to each model is executed by the logic to be verified, and the execution result is the result comparison function of the verification program itself. Have confirmed by. Moreover, in the batch compare method of the execution result in the single instruction sequential execution type instruction simulator and the execution result in the logic to be verified, the cause of the mismatch is that the single instruction sequential execution type instruction simulator Since it is a sequential processing of, it was realized by analyzing whether or not the disagreement occurred by manual intervention. As a related conventional technique of this type, for example, the technique described in Japanese Patent Laid-Open No. 5-67966 is known.

[0003]

In the prior art, the result comparison processing routine collectively compares the execution result (expected value) of the single instruction sequential execution type instruction simulator and the execution result of the verified logic, and When the contents do not match, the cause of the mismatch will be manually investigated based on information such as an error message. However, it is necessary to examine the instruction trace, the logic execution trace, etc. to determine whether this inconsistency is caused by the prefetch of the RAM by the preceding control of the logic to be verified or the logic to be verified is defective. is there. Such inconsistencies frequently occur even in a verification program (single instruction test or the like) that does not target the preceding control for verification, and it is unavoidable to prevent batch compare of RAMs. Therefore, only the inconsistency generated in the verification program in which the update control of the RAM is verified is investigated by manual intervention. In this investigation, since manual intervention is involved, it is difficult to analyze because the verification contents (test instruction sequence, target RAM state, etc.) and the logic to be verified have to be grasped.
Further, it is impossible to guarantee whether or not the RAM update control is appropriate only with some of these verification programs, which is one of the factors that make it difficult to extract a logic defect. An object of the present invention is to solve the above-mentioned problems and to use a batch conveyor method in which all RAM compare mismatches occur only when a true mismatch occurs (when a defective logic to be verified is detected) is used in all verification programs. , To provide a highly accurate verification method.

[0004]

To achieve the above object, the present invention stores a logic simulator for executing a logic verification program, a single instruction sequential execution type instruction simulator, and an execution result of the logic simulator. A result value file, an expected value file for storing the execution result of the single instruction serial execution type instruction simulator, a batch compare means for comparing the stored content of the result value file and the stored content of the expected value file, and the means Is a logic simulation verification method that includes a batch compare result file that stores the output of the pre-fetching of instructions that are executed by the logic simulator but not executed by the single-instruction sequential execution type instruction simulator, data prefetch, and in the same column. It is accompanied by cache such as RAM competition, and processing to update the contents of TLB. The preceding processing condition file storing the contents of the processing corresponding to the instruction address of the instruction is connected to the single instruction sequential execution type instruction simulator, and the single instruction sequential execution type instruction simulator executes the instruction every time the instruction is executed. Search the preceding processing condition file by address,
When the content of the corresponding process is fetched, the RAM update including the prefetched instruction address, the target address at the time of data access, the initial value of the data cache column to be updated, etc. based on the content of the process Generate data, R
It is registered in the AM update data file. Further, if the result of the comparison by the batch compare means is that they do not match, a warning is displayed when the contents of the mismatch are registered in the RAM update data file, and an error is displayed when they are not registered. There is. Further, the logic simulator is used as an actual data processing device.

[0005]

By the above means, it becomes possible to automatically check the validity of the contents update of the RAM, which has been conventionally confirmed by manual intervention. As a result, it becomes possible to confirm the test results in a shorter time than before, and it is possible to improve the verification accuracy by applying it to the running of all test programs.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a process for checking the validity of updating the contents of a RAM according to an embodiment of the present invention and executing a batch comparison of test results. (1) The logic simulator (development processor operation simulator described in wiring-level intermediate language) 101 executes the verification program 100 and collects the execution result in the result value file 104.

(2) The single instruction sequential execution type instruction simulator 102 executes the verification program and collects the execution result in the expected value file 105. For example, when the logic simulator 101 executes a Branch instruction, as shown in FIG. 2, a process of prefetching the following eight instructions that are not executed subsequent to the Branch instruction into the instruction cache is already performed. However, since the single-instruction successive execution type instruction simulator 102 reads and executes one instruction at a time, it does not prefetch the instruction to the instruction cache. Therefore, in the preceding processing condition file 103, the Br executed by the single instruction sequential execution type instruction simulator 102 is
The instruction address of the inch instruction and the prefetch processing content a to be executed by the logic simulator 101 corresponding to the instruction address are stored in advance, and the single instruction sequential execution type instruction simulator 102 stores each instruction address to be executed. The preceding processing condition file 103 is searched. Processing content a: Branch Code Cache = +
8 When the instruction executed by the single instruction sequential execution type instruction simulator 102 is a Branch instruction and the instruction address matches the instruction address stored in the preceding processing condition file 103, the instruction is read from the preceding processing condition file 103. The processing content a corresponding to the address is read. When the processing content a is read, the single instruction sequential execution instruction simulator 102 includes the instruction address next to the address of the Branch instruction, for example, the following RAM.
Update data Code CacheCLM = 1, EV = 1, ADR =
100, DATA = 012F is generated and registered in the RAM update data file 106. The above processing is performed by prefetching instructions by the logic simulator, prefetching data, and RA in the same column.
The process for updating the contents of the cache and TLB, such as M contention, is performed in the same manner.

(3) The result value file 104 and the expected value file 105 are collectively compared 107.

At this time, if the contents of the RAMs do not match, R
By referring to the AM update data file, a warning display is output to the batch comparison result file 108 if it is the target RAM for which the conditions are registered, and an error display if it is the non-target RAM.

FIG. 3 shows the preceding processing condition file reference and R
9 is a flowchart showing an AM update data file registration process. Hereinafter, each step of FIG. 3 will be described in detail. When an expected value is generated by the single instruction sequential execution type instruction simulator 102, the instruction execution sequence is sampled as an instruction execution trace. At this time, if the instruction address becomes non-contiguous due to branching or interruption, it is assumed that the advance control works and the instruction cache is prefetched, and the subsequent address of the instruction that generated the non-contiguous address is also cached. May have been taken into. The single instruction sequential execution type instruction simulator 102 searches and checks the preceding processing condition file 103 according to the instruction address to be executed (201). If non-contiguous instruction addresses are generated, the RAM update data including the instruction address next to the instruction address causing the non-contiguousness is registered in the RAM update data file (202). In addition, assuming that the execution result of the last executed instruction does not remain in the cache due to the data access execution, the instruction before and after the prefetch access to the data cache (prefetch operation to the data cache), etc. When an instruction whose execution order is not guaranteed is executed, the preceding processing condition file 103 is searched and checked by the instruction address to be executed (203). as a result,
If there is a match, the RAM update including the target address at the time of data access is registered in the RAM update data file (204). Further, assuming that the data cache columns to be updated conflict due to the data access execution and the data access execution is invalidated, the data access execution is performed by another continuous data access. When updating the same cache column as execution, the preceding processing condition file 103 is searched and checked by the instruction address to be executed (205). As a result, if there is a match, the RAM update data including the initial value of the update target data cache column is set to R.
It is registered in the AM update data file (206).

FIG. 4 is a flow chart showing the RAM update data file reference processing. Hereinafter, each step of FIG. 4 will be described in detail. The result value file 104 created by the logic simulator 101 and the expected value file 10 created by the single instruction sequential execution type instruction simulator 102.
5 are compared (301), and if they match, it is determined to be normal, and the batch comparison result is displayed (306). In the case of disagreement, if the content of the disagreement is registered in the RAM update data file (302), a warning is displayed (304) and the error is not treated as the compare result. Registered data
The mismatches other than the above are classified as either an expected value defect (a defect on the single instruction sequential execution type instruction simulator side) or a result value defect (a defect on the verified logic side), and an error display (303). ). RAM update data 305 is attached as attached information in this case and used for failure analysis.

The above processing contributes to shortening of failure analysis time due to occurrence of mismatch in the comparison result and improvement of verification accuracy when applied to all verification programs.
Although one embodiment of the present invention has been described above, the batch compare method can be applied to an actual data processing device as well as the logic simulation.

[0013]

As described above, according to the present invention, it is possible to efficiently and accurately perform logic verification on a logic simulator or an actual data processing device which is a logic verification target. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a process of performing a validity check of a content update of a RAM and executing a batch comparison of test results.

FIG. 2 is a diagram showing an instruction prefetch state by a logic simulator at the time of executing a Branch instruction.

FIG. 3 RA in a single instruction sequential execution instruction simulator
It is a figure which shows the flowchart of generation of an M update data file, and registration processing.

[FIG. 4] Batch compare processing and R in the result comparison module
It is a figure which shows the flowchart of the reference method of the RAM update data file and the process of validity check when the comparison result of AM does not match.

[Explanation of symbols]

 100 Verification Program File 101 Logic Simulator 102 Single Instruction Sequential Execution Type Instruction Simulator 103 Preceding Processing Condition File 104 Result Value File 105 Expected Value File 106 RAM Update Data File 107 Compare Processing 108 Batch Compare Result File

Claims (3)

[Claims] 1. A logic simulator for executing a logic verification program, a single-instruction sequential execution type instruction simulator, a result value file for storing execution results of the logic simulator, and execution of the single-instruction sequential execution type instruction simulator. According to the logic simulation verification method, an expected value file for storing a result, a batch compare means for comparing the stored content of the result value file with the stored content of the expected value file, and a batch compare result file for storing the output of the means. Therefore, prefetching of instructions executed by the logic simulator but not executed by the single instruction serial execution type instruction simulator, data prefetch, cache such as RAM conflict in the same column, and processing for updating the contents of TLB are performed. Stores the contents of the process corresponding to the instruction address of the accompanying instruction The preceding processing condition file is connected to the single instruction serial execution type instruction simulator, and the single instruction serial execution type instruction simulator searches the preceding processing condition file by an instruction address every time an instruction is executed, and responds. When the content of the processing is fetched, based on the content of the processing, the prefetched instruction address,
Target address during data access, update target data
A logic simulation verification method characterized in that RAM update data including initial values of data cache columns is generated and registered in a RAM update data file. 2. The logic simulation verification method according to claim 1, wherein when the result of the comparison of the batch compare means is a mismatch, a warning is displayed when the content of the mismatch is registered in the RAM update data file. , A logic simulation verification method characterized by displaying an error when it is not registered. 3. The logic simulation verification method according to claim 1, wherein the logic simulator is an actual data processing device.