JPH07306809A - Verifying method of data processor - Google Patents

Abstract

PURPOSE:To provide the verifying method of the data processor which can specify or estimate a data destruction position in a cache memory. CONSTITUTION:The data processor which has cache memories 2 and 3 in multi- layered structure saves data before test instruction execution in another area in a cache memory in the same layer, and compares an expected value and a saved expected value, execution data and the expected value, saved execution data and the expected value, the expected value and execution data in a high- layer cache memory 2 and execution data in a low-layer cache memory 3 right after test instruction execution and after execution result (PSW and register information) reaping to verify which part of a cache memory in which layer data destruction is caused judging from the generation of a discrepancy. Consequently, the cache memory and its position which causes malfunction due to the data destruction can efficiently be efficiently specified or estimated in a short time by checking the he execution result of software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device verification method, and more particularly to a data processing device verification method for verifying data destruction of a cache memory.

[0002]

2. Description of the Related Art As a technique for supporting high performance of a data processing apparatus, there is a pipeline control method in which an instruction is decomposed into several processing steps (stages) and each apparatus processes a specific stage every machine cycle. Widely adopted.
The pipeline processing, which is also called the advanced control function, is realized by complicated and large-scale logic, and the degree of advanced control is extremely deep. Pipeline processing,
Control of buffer memories related to transfer of instructions and data as well as calculation is included.

Conventionally, in a verification program for the purpose of logic verification, even in the pipeline processing in which the above pipeline processing operates at the same time, a failure (garbled data, destruction) occurs in cache memory related to instructions and data transfer. In that case, the search for the cause was extremely complicated and extremely difficult.

At our company, an operation verification method has been proposed for the advance control of the states of various cache memories inside the hardware. For example, even if the cache memory is garbled, it is necessary to manually investigate the cause. A lot of time is spent, and defects (garbage of data, destruction) can be detected, but the analysis capability is insufficient.

[0005]

In the above-mentioned prior art,
At the first execution of the test instruction sequence, since the instruction and data are not transferred from the main storage device to the various memories inside the hardware, the advance control function operates slowly, and at that time, the main memory is stored in various buffers. When the instruction and data are transferred from the device and the instruction is executed, and the second same test instruction sequence is executed,
The instructions and data are executed by using the instructions and data in various cache memories in the hardware without fetching the instructions and data from the main storage device. In this way, the combination test of the advanced control function and the state of the cache memory inside the hardware is carried out under different environments.

However, when a defect (garbled data or destruction) occurs during execution of a test instruction, it is difficult to identify the defective portion, and a stage tracer (logic signal tracer) or the like included in the hardware is used. There is a great deal of reliance on manual analysis.

An object of the present invention is to solve or solve the above-mentioned conventional problems, and to identify or estimate the cache memory and the part which have caused data garbled in various cache memories at the time of executing a test instruction or malfunction due to data destruction. To provide a possible data processing device verification method.

[0008]

According to the verification method of the data processor of the present invention, in verifying the location of the data destruction in the cache memory having the multi-layer structure such as the two layers and the three layers, first, immediately after the execution of the test instruction, Test data saving means for saving the expected value for verification and the execution data to another area in the same cache memory, and the execution result (PSW,
Register information) After pruning, the expected value and the expected value saved in the same level cache memory, the execution data and the expected value, the saved execution data and the expected value, and this expected value and the execution data in the upper layer cache memory, the lower layer cache It has an execution result judging means for comparing the execution data of the memory with each other and detecting it as a data destruction portion when a mismatch occurs.

[0009]

According to the present invention, when a defect (garbled data or destruction) occurs during execution of a test instruction, the cache memory and the part that cause the malfunction of data in various cache memories or the malfunction due to data destruction are identified. Alternatively, the estimation was changed to the conventional method of manually using a measuring instrument, and it was made possible by executing software.
As a result, it is possible to significantly reduce the number of personnel and the time required to detect the data destruction occurrence site.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system showing an embodiment of the present invention. When executing an instruction, as described above, the instruction and data are transferred from the main memory 5 to the system controller 4
It is transferred to a cache memory called a work memory 3 in the above, further transferred to a cache memory called a buffer memory 2, and then executed by the instruction processor 1.

FIG. 2 is a block diagram showing an embodiment of the present invention. The verification method of the data processing device has a test instruction executing means 21, a test data saving means 22, and an execution result judging means 23.

A test instruction executing means 21, a test data saving means 22, a verification program 20 including an execution result judging means 23, and a monitor program 10 are stored in the main storage device 6.

FIG. 3 shows the internal structure of the buffer memory 2 and the work memory 3 of FIG. In this cache memory, a position for storing data is designated by a column and a ROW.

FIG. 4 is a flow chart showing the processing of the verification program 20 for verifying the cache memory.

First, the monitor program loads the verification program 20 into the main storage device 5, and the verification program 2
Start 0. The activated verification program performs the processing shown in FIG.

When the test instruction is executed in the process 100,
Execution data 80 is stored in the lower layer cache memory of FIG. 3, and effective data 60 having the same content as the effective data 80 is stored in the upper layer cache memory.

In process 101, the test data is saved immediately before the instruction to be tested is executed, and as shown in FIG. 2, the expected value 50 of the verification target cache memory is changed to the expected values 51 and 52 and the execution data 60. The effective data 61,6
A plurality of files are saved in an arbitrary area, such as to 2.

Immediately after the execution of the test instruction, the process 102 prunes the execution result (PSW, register information) of the test instruction.

In process 103, the expected value 50 shown in FIG.
When the saved expected values 51 and 52 are compared with each other and a mismatch occurs, the compared data has been destroyed, so the process 104
Then, the process moves to the step, and the data position and contents in the cache memory used in the test at this time are output as error information, and the process ends.

If the expected value 50 and the saved expected value 5
If there is no discrepancy in the comparison with 1,52, the expected value is 5
When 0 is compared with the effective data 60, 61, 62 and the effective data 80 of the lower layer cache memory and a mismatch occurs,
Since the compared data is destroyed, the process proceeds to step 104, and the data position and contents in the cache memory used in the test at this time are output as error information, and the process ends.

Next, the detection of a data destruction portion in this method will be described with a specific example.

First, immediately before the execution of the test instruction to be tested in the test instruction sequence in which the advance control mechanism operates, for example, the execution data 60, which is the input data of the test instruction shown in FIG.
It is assumed that, for example, '9999' is recorded in, and '9999' is recorded in the expected value 50 which is the expected value of the execution data 60. Subsequently, the test data is saved and the execution data 6
The execution data 60 is saved in the areas 1 and 62. The expected value is not used for the calculation of the test instruction, but as a precaution, the expected value 51,
The expected value 50 is saved in 52.

Immediately after the execution of the test instruction, the expected value 50 and the saved expected values 51 and 52 are compared to confirm the validity of the data.

Next, the expected value 50 and the execution data 60, 6
Compare 1,62. Normally, execution data 60, 6
The areas 1, 62 are available only when the test instruction is completed and the subsequent instruction is executed, so the contents of the execution data 60, 61, 62 at this point are '9999'. .

However, at this time, if the execution data 60 is, for example, "5555", the data is destroyed at the location of the execution data 60 due to any instruction processed by the preceding control mechanism or some defect. You can see that

Further, as described above, since the same value as the execution data 60 is stored in the execution data 80 of FIG. 3,
For example, the execution data 60 above is not "5555", but "
If 9999 'matches the expected value 50 of' 9999 'and the execution data 80 is, for example,' 4854 ', the location of the execution data 80 is due to any instruction processed by the preceding control mechanism or some defect. You can see that the data has been destroyed by.

Although the present embodiment has been described by using the cache memory of three layers, the same idea is applied to the verification of the cache memory of two layers or other multiple structures.

[0029]

As described above, according to the verification method of the data processing device of the present invention, by observing the execution result of the software, it is possible to identify or estimate the cache memory and the part that cause the malfunction due to the data destruction. The effect is that it can be done efficiently in a short time.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a system showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an internal configuration of a buffer storage 3 and a work storage 5 of FIG.

FIG. 4 is a flow chart showing processing of a verification program using the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Instruction processor, 2 ... Buffer storage, 3 ... Work storage, 4 ... System control device, 5 ... Main storage device, 10 ... Monitor program, 20 ... Verification program, 21 ... Test instruction execution means, 22 ... Test data saving means , 23 ... Execution result judging means, 50 ... Expected value, 51 ... Expected value, 52 ... Expected value, 60 ... Execution data, 61 ... Execution data, 62 ... Execution data, 80 ... Execution data, 100 ... Test instruction execution process, 101 ... Test data saving process, 102 ... Test instruction execution result pruning process, 103 ... Cache memory execution result judging process, 104 ... Error information output process.

Claims (1)

[Claims] 1. In a data processing device having a cache memory having a multi-layer structure such as two layers and three layers, data immediately before execution of a test instruction is saved in another area in the same-layer cache memory, and immediately after execution of the test instruction. , After the execution result (PSW, register information) has been pruned, the expected value and the saved expected value, the execution data and the expected value, and the saved execution data and the expected value are compared, and a mismatch occurs, so that data in the same-tier cache memory By verifying the location of the destruction and comparing the expected value with the execution data of the upper-layer cache memory and the execution data of the lower-layer cache memory, and a mismatch occurs, the data corruption occurs in which cache memory. A verification method for a data processing device characterized by verifying whether it has occurred.