JPH01214950A - System for testing pseudo fault of channel processor - Google Patents

Abstract

PURPOSE:To easily investigate the cause of the generation of abnormality by performing an input-output process after setting a pseudo fault in a channel processor and, when the result is normal, storing the pseudo fault and results obtained when the pseudo fault exists of the pseudo fault, and then, performing tests by using the pseudo fault as a testing condition. CONSTITUTION:A pseudo fault is set in a channel processor 5 by using a service processor 7 and a CPU 1 is allowed to execute an input-output process by actuating the processor 5. When obtained results are normal, the pseudo fault and results obtained when the pseudo fault exists are stored in a storing means 3 and a pseudo fault test is performed by using the pseudo fault as a testing condition. When the operation results against thus set pseudo faults are successively accumulated, results against the pseudo fault can be predicted and the implementation of a test program becomes unnecessary. Therefore, the cause of the generation of abnormality can be investigated easily.

Description

[Detailed Description of the Invention] [Summary] A processor comprising a central processing unit, a channel including a channel processor for connecting the central processing unit and an input/output device, and a service processor for testing a system. Concerning a pseudo-failure test method for channel processors in systems, the purpose is to perform pseudo-failure tests on channel processors without predicting operational results due to pseudo-faults. setting, and then the central processing unit starts this channel processor to execute input/output processing, and if the processing results obtained are normal, this pseudo failure and this pseudo failure occur. The results were stored in a storage means, and a simulated failure test was conducted using this simulated failure as a test condition.

[Industrial application field]

The present invention relates to a simulated failure test method for a channel processor in a processor system including a processor, a channel processor for connecting the processor and an input/output device, and a service processor for testing the system.

[Conventional technology]

FIG. 3 shows an example of a processor system to which the channel processor pseudo-failure test method according to the present invention is applied. This channel 4 has multiple input/output devices 63.6.
2. ...6n is connected.

A service processor 7 for testing and monitoring the central processing unit 1, main memory 3, channel 4, etc. is further connected to the MCU 2, and this service processor 7 has a keyboard for inputting data. 8, a display device 9 for output, a printer 10, etc. are provided.

FIG. 4 is a flowchart showing an example of a conventional method for testing the RAS function of the channel processor 5 which covers the abnormality and notifies the central processing unit 1 when an abnormality occurs in the channel 4 or the input/output device. It was shown as

In this FIG. 4, the first test process T,...
In step ■, the service processor uses a program prepared in advance to set a pseudo fault in the channel processor, and then in step The operation result, such as whether or not the expected channel processor operation was carried out, is determined in step (3).

If the processing result is determined to be abnormal in this step ■, the occurrence of an error will be displayed in step ■, and if the result is determined to be normal in this step ■, then directly as above. A second test process T2 consisting of steps ① to ② is executed.

In this way, the RAS function of the channel processor is tested by repeating steps (1) to (2) as one test processing unit for a plurality of predetermined pseudo faults up to the test process Tn for the final pseudo fault.

In such conventional channel processor pseudo-fault test methods, if the system hardware configuration is changed or a point where a pseudo-fault is set is added, the test results must be predicted. There is a problem in that it is necessary to modify or add to the test program, which not only requires a lot of man-hours but also increases the scale of the program.

In addition, even if an abnormality occurs, only a pseudo fault and its result are known, but the cause cannot be ascertained, and the result of actual operation does not necessarily match the above prediction.

[Problem to be solved by the invention]

The present invention eliminates the prediction of operation results due to pseudo-failures as described above, and thereby enables
The purpose is to enable pseudo-impairment tests to be conducted.

[Means to solve the problem]

A central processing unit 1, this central processing unit and an input/output device 6.
．． 62. ...6n, and a service processor 7 for testing the system. A pseudo failure is set, and then the central processing unit starts this channel processor to execute input/output processing, and if the obtained processing result is normal, this pseudo failure and this pseudo failure occur. The obtained results are stored in a storage means, and a simulated failure test is conducted using this simulated failure as a test condition.

[For production]

FIG. 1 is a flowchart for explaining the present invention in detail.
The test mode and the content of the pseudo failure to be set are entered by inputting from the keyboard (FIG. 3, FIG. 8) shown in FIG. 3 (FIG. 3, 7) or by using a program created based on previous test results.

In step [2], it is determined whether or not this is an instruction to end the simulated fault test. If the test is not completed, the above-mentioned simulated fault settings are made in step [3], and in the following step [4], the central processing unit The channel processor (FIG. 3, 5) is caused to perform input/output operations according to instructions from the channel processor (FIG. 3, 1).

It is determined in step [5] whether the test mode is the error cause investigation mode, and if it is the error cause investigation mode,
In step [11], the operation of the channel processor is stopped according to the preset processing steps, and in step [12], the cause of the error is investigated, and in step [13], the content of the pseudo failure and its execution result are determined. After accumulating , the process continues by returning to step 2 and setting the next pseudo failure.

If the result determined in step [5] above is not the error cause investigation mode, the result of the input/output operation performed in step [6] is displayed on the service processor display (Fig. 3, 9).
In step [7], it is determined whether the operation result is normal based on the tester's analysis or the results of previous executions.

If it is normal, in step [8], this pseudo fault and the corresponding results are stored as normal results for the set pseudo fault so that they can be added as test data of the test program, but if If it is determined in step [7] that the operation result is abnormal,
In step [21], the above-mentioned display or printer (Fig. 3, 10) of the service processor displays that there is an error or further details of the error;
Furthermore, in step [22], switch the test mode to error cause investigation mode, return to step [2] above, and repeat the process from step [4] onwards without changing the settings of this pseudo failure to investigate the cause of the error. conduct.

In this way, by sequentially accumulating the operation results of the channel processor for the set pseudo faults, there is no need to predict the results for the pseudo faults and create a test program. This makes it easier to investigate the cause.

〔Example〕

FIG. 2 is a flowchart showing an embodiment of the present invention. In step (2), as a preprocessing, an input/output device that can be activated is extracted, and a test is performed by inputting from the keyboard or read from a specified storage device. Select whether to conduct the test using the program.

In step (2), as in step [1] of Fig. 1, information necessary for setting a pseudo fault to the channel processor is input, and in step (2), the pseudo fault is set as a diagnostic command execution step. Then, in step (3), the central processing unit causes the channel processor to execute input/output instructions.

In step 2, if the test mode is set to the error cause investigation mode as explained with reference to FIG. Step [12
], Similar to [13], after investigating the cause of the error and accumulating test data in step 0.0, return to step (2).

If it is determined in the above step (■) that the error cause investigation mode is not in effect, the execution result of the channel processor is displayed on the display or printer of the service processor in step (2), the execution result is determined in step (2), and the result of this determination is displayed. If there is an abnormality, an error message is output from the printer of the service processor in step 0, and in step Φ, the error cause investigation mode is set to investigate the cause of the error, and the above step
Return to

If the result is normal according to the judgment of the execution result in step ■ above, the pseudo failure set in step ■ and the result obtained by this pseudo failure are used as data for the next test, and in step ■, for example, It is stored on a storage medium such as a magnetic disk.

In the next step (2), it is determined whether all the test contents have been completed, and if so, the test is terminated, and if not yet, the process returns to step (2) and the next test contents are executed.

〔Effect of the invention〕

According to the present invention, by accumulating the operation results of channel processors for pseudo faults, there is no need to predict the results for pseudo faults and create a test program, and even if an abnormality occurs, the cause can be investigated. It is possible to achieve a special effect of making it easier.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the principle of a channel processor pseudo fault test method according to the present invention, FIG. 2 is a flowchart showing the operation of an embodiment of the present invention, and FIG. 3 is a flowchart showing the configuration of a processor system to which the present invention is applied. FIG. 4 is a flowchart illustrating an example of a conventional channel processor pseudo fault test method.

Claims (1)

[Claims] A channel including a central processing unit (1) and a channel processor (5) for connecting the central processing unit and input/output devices (6_1, 6_2, . . . 6n). (4)
and a service processor (
7) In a processor system equipped with the above service processor, a pseudo failure is set in the channel processor, and then the central processing unit starts this channel processor to execute input/output processing, and the obtained processing result is normal. If the simulated failure occurs, the simulated failure and the results obtained in the event of this simulated failure are stored in the storage means, and a simulated failure test is conducted using the simulated failure as a test condition. A simulated failure test method for channel processors.