JPH01134539A - Trace system for microprogram - Google Patents

Abstract

PURPOSE:To reduce an action test process for a microprogram by extracting preliminarily the address of a microinstruction to be executed and detecting the coincidence between said address and the address of a microinstruction under execution. CONSTITUTION:Plural microinstructions to be executed are preliminarily extracted and the addresses of these microinstructions are stored successively in an estimated address storing buffer 11 in the processing order. Then the address of the microinstruction to be processed first is stored in an estimated address register 12. Then a test program is carried out and the value of an address register 6 is compared with that of the register 12 by a comparator 10. When the coincidence is obtained from said comparison, the next estimated address is stored into the register 12 via the buffer 11. These actions are repeated and it is checked whether any address remains in the register 12 or not when the program processing is through. Thus a malfunction can be detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram tracing method for testing the operation of a microprogram.

[Conventional technology]

Conventional microprogram tracing methods include the following.

(1) The number of bits of a microinstruction is expanded to include a bit that indicates the execution method of the instruction, and when one microinstruction is executed, by setting the execution method display bit, the execution method can be set during one process. A method for checking microinstructions.

(2) A method in which an expected value of the data to be written as a result of executing the processing instructed by the test program is created, and the data value obtained when the test program is actually executed using the ratio test microprogram is compared with the above-mentioned expected value. .

(3) Create software that replaces the main hardware functions of an information processing device, apply that software to a simple device, and have it execute various instructions to determine the microprogram when executing one step. A method (simulation method) of tracing all executed micro-instructions such as addresses, data held by various registers, data stored in local memory, etc. [Problems to be solved by the invention] The above-mentioned conventional microprogram Each tracing method has the following drawbacks.

The first tracing method is a method that sets the executed indication bit of the executed microinstruction, so it is not possible to determine the number of times the same microinstruction with the executed indication bit set is executed. If the above tests are executed continuously, it is not possible to determine the operation of the microprogram in each test.

The second tracing method confirms the normality of the operation by comparing the results of executing the test program with the expected values, so it is necessary to check the detailed operation of the microprogram from the start of execution to the end of the test program. I can't.

The third tracing method is a simulation test using a software method, so it is possible to obtain detailed data for each step, but the number of software steps is enormous, and it takes a long time to simulate one process. It is time consuming, and furthermore, it takes a lot of man-hours to trace and analyze the results.

[Means for solving problems]

The microprogram tracing method of the present invention is as follows.

Extracting in advance a plurality of addresses in a storage device of microinstructions that are predicted to be executed in the microprogram according to test contents instructed by a test program, and storing the extracted predicted addresses; Start the test program and start processing the test contents, retrieve the stored predicted addresses from the earliest in the processing order, compare them with the address of the microinstruction being executed, and compare the predicted address with the address of the microinstruction being executed. When a match with the address of the executed microinstruction is detected, the first predicted address is extracted and compared with the currently executed microinstruction, and this comparison operation is sequentially repeated until all the predicted addresses match the address of the executed microinstruction. By detecting whether or not the operation of the microprogram is normal or abnormal, it is determined whether the operation of the microprogram is normal or abnormal.

[For production]

Since the operation of the microprogram is tested by determining whether all the microinstructions at the predicted addresses are executed in a normal operation sequence, the test results can be obtained immediately.

Since the test does not use a software method like the conventional simulation method, the number of man-hours can be significantly reduced, and it is also possible to test multiple processes in succession.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an input/output device for implementing the microprogram tracing method of the present invention, FIG. 2 is a block diagram showing the configuration of an information processing system in which the input/output device of FIG. 1 is used, and FIG. 3 is a diagram showing an example of the operation sequence of the microprogram in the input/output device of FIG. 1, FIG. 4 is a diagram showing the format of a predicted address group stored in the main memory, and FIG. 3 is a flowchart showing the procedure of a program trace method.

The information processing system in FIG. 2 includes a main storage device 17, a CP
The main memory controller t19, a diagnostic device 20 that diagnoses the normality of the operation of the microprogram, and an input/output processing device 21. Note that in this embodiment, the term input/output device is used as a broad concept that includes channel devices and channel control devices. On the Kinomi side, an operation test of the microprogram in the input/output device 21 will be explained.

In the input/output device 21, a microprogram to be tested is stored in a microprogram storage memory 1, an address register 6 holds the address of a microinstruction to be read from the microprogram storage memory 1,
Microinstruction register 2 holds microinstructions read from microprogram storage memory l. The next address register 3 holds the jump destination address already stated in the microinstruction, the increment address register 4 holds the address incremented by the arithmetic unit 7, and the selector 5 holds the address that the next address register 3 and increment address register 4 hold. One of the addresses is selected and sent to the address register 6 and the arithmetic unit 7. The predicted address par/2a 11 for storing predicted addresses stores the predicted address read from the main memory 17, and the predicted address register 12 holds the predicted address read from the address buffer 11 for storing predicted addresses. The predicted address register 13 stores the final predicted address among the predicted addresses. Address register 8 holds write/read addresses of address buffer 11 for storing predicted addresses. Comparison circuit 1
0 is the value of address register 6 and predicted address register 1
2 and when they match, an increment signal is sent to the arithmetic unit 9 and a match signal is sent to the AND circuit 15, respectively. When the arithmetic unit 9 receives the increment signal from the comparison circuit 10, it increments the value of the address register 8 and sets it in the address register 8 again. The comparison circuit 14 compares the value of the predicted address register 12 and the value of the final predicted address register 13, and when the two match, it sends a match signal to the AND circuit 15. The product is calculated, and if a matching signal is sent from both comparison circuits, a normal sequence display flag 18 is set.

Next, the procedure for testing the operation of the microprogram stored in the microprogram storage memory 1 and the circuit operation of the input/output device 21 will be explained.

Before starting the microprogram operation test, first
The diagnostic device 20 creates a predicted address group 22 in the format shown in FIG.
17 to memorize it. This predicted address group 22 consists of five events (input/output request 30, command sending 40, data transfer 50, status report 60, end interrupt 70: these events are executed in the order of 30 to 70). A plurality of appropriate microinstructions are extracted from among the microinstructions 31 to 7n that constitute each event in the microprogram, and the physical address a- of each extracted microinstruction is
n are arranged in descending order of first profit, and are stored in the main storage device 17 in this order.

Next, the diagnostic device 20 sends an input/output request to the input/output device 21 in order to start the test program.

When the input/output processing device 21 receives this request, it starts processing for the event 30 (input/output request processing), and first,
The predicted address group 22 stored in the main storage device 17 is stored in the address buffer 11 for storing predicted addresses, and the final predicted address n is stored in the final predicted address register 13 (stave 100), for storing this predicted address. When storing data in the address buffer 11, the address register 8 starts specifying an address from address zero under the control of the microprogram, and the final predicted address group 22 (
a to n) are stored sequentially starting from address zero. Furthermore, when the storage of the predicted address group 22 is completed, the address register 8
is cleared and points to the first address (zero address).

Next, the input/output device 21 executes the test program, which is sequentially read from the microprogram storage memory l, and is controlled by the microinstructions sent from the microinstruction register 2 to perform predetermined processing. At this time, the value of the address register 6 and the value of the predicted address register 12 are compared in the comparison circuit 10 (step 101), and when the values of both registers 6 and 12 match, an increment @ sign and a match signal are generated, and an increment signal The coincidence signal is sent to the AND circuit 15 and the arithmetic unit 9, and in response to this, the value of the address register 8 is incremented. This allows predicted address register 1
2 is set to the next predicted address (step 10
3) At the same time, the value of the address register 6 is updated, and the next microinstruction is set in the microinstruction register 2. In this case 1, normally, the value incremented by the arithmetic unit 7 and held in the increment address register 4 is set in the address register 6 via the selector 5, but if a jump address is specified in the microinstruction, , the jump address is set in the address register 6 via the junk 5, and six or more operations are sequentially repeated. It is detected whether or not the values match (step 102), and when a match is detected, a match signal is sent from the comparison circuit 14, and the comparison circuit 10 and ! If a match signal is generated from 4 to 4, the AND circuit 15 turns on the normal sequence display flag IB (step 104), indicating that all predicted addresses operate normally even though all microinstructions have been executed. If not in sequence, the predicted address where the malfunction occurred is predicted address 12.
The diagnostic device 20 stores this in the main memory bag 2117 (step 105).
When the processing of the two test programs is completed, check whether the normal sequence display flag 1B is on (step toe), and if it is on, output a normal meta message (step 107) or start the next input. An output request is sent, and if it is in the off state, an error message is displayed and the final value of the predicted address register 12 stored in the main memory 17 is read and displayed (step 108''), and the operation test is completed.

〔Effect of the invention〕

As explained above, the present invention extracts a plurality of addresses of microinstructions that are predicted to be executed in the microprogram under test according to the test contents instructed by the test program, executes the operation test, and simultaneously executes the actual The primary effect is to check whether all microinstructions at the predicted addresses are executed in a normal sequence and to display or output the results through a diagnostic device.

(1) For the purpose of tracing the operation sequence of a microprogram, it is not necessary to trace the address of the executed microinstruction every time one process is completed, and a plurality of processes can be tested in succession.

(2) The normality of the operating sequence of a microprogram, which cannot be confirmed simply by comparing the execution result with an expected value, can be instantly determined based on an error message or the like from the diagnostic device.

(3) Many man-hours required for checking the operation sequence of a microprogram through simulation can be reduced.

(4) If the microprogram's operation deviates from the expected sequence during an operation test, the diagnostic equipment can determine how far it is operating in the normal sequence by referring to the address retrieved from the device under test (main memory). You can judge whether

[Brief explanation of the drawing]

Figure 1 is a flow diagram of an input/output device for implementing the microprogram tracing method of the present invention, and Figure 2 is a
A block diagram showing the configuration of an information processing system in which the input/output device shown in the figure is used, FIG. 3 is a diagram showing an example of the operation sequence of a microprogram in the input/output device shown in FIG. FIG. 5 is a flowchart showing the procedure of the microprogram tracing method of the present invention. l...Memory for storing microprograms, 2...Micro instruction register, 3...
...Next address register, 4...
...Increment address register, 5...
... Selector, 6.8... Address register, 7.9... Arithmetic unit, 10.14... Comparison circuit. 11... Address buffer for storing predicted address 12... Predicted address register,
13...Final prediction address register, 1
5......AND circuit, 1B.......Normal sequence display flag. 17... Main memory. 18...CPU, 19...Main memory control device, 20...
...Diagnostic device, 21...Input/output processing device, 22...
...Predicted address group. 30.40.50,80.70...event,
31-7n...Microinstruction, aNn...Predicted address, 100-108...Step. Patent applicant: Hiki Electric Co., Ltd. Agent: Susumu Uchihara, patent attorney M2 diagram

Claims (1)

[Claims] A microprogram tracing method for testing the operation of a microprogram by executing a test program on an information processing device that operates under microprogram control, the method comprising: A plurality of addresses in the storage device of microinstructions that are predicted to be executed in the microprogram are extracted in advance, the extracted predicted addresses are stored, and the test program is started to check the test content. starts processing, extracts the stored predicted addresses from the earliest in the processing order and compares them with the address of the microinstruction being executed. When a match between the predicted address and the address of the microinstruction being executed is detected, , the next predicted address is retrieved and compared with the microinstruction being executed, and this comparison operation is sequentially repeated to detect whether all predicted addresses match the address of the executed microinstruction. A microprogram trace method that determines whether the operation is normal or abnormal.