JPH0214734B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In an information processing device that processes in a pipeline system and is equipped with a serialization instruction processing mechanism, a test instruction sequence containing only general instructions and a test instruction sequence containing serialization instructions are processed. The processing results obtained by inputting a test instruction sequence of only general instructions prepared on the main memory and read from the main memory into the pipeline, serialized instructions, and multiple general instructions are alternately processed. By comparing the processing results obtained by inputting the arrayed test instruction sequences into the same pipeline, the fault location in the pipeline mechanism is identified.

[Industrial application field]

The present invention relates to a method for testing a pipeline mechanism in an information processing apparatus that performs processing using a pipeline method.

With the remarkable spread of computer systems (information processing devices) in recent years, the amount of data processed by computer systems has increased, and as a result, the demand for improving the processing capacity of these computer systems has become increasingly high. .

As one method for improving the processing capacity of computer systems, a method of inputting a plurality of instructions into a pipeline and executing a plurality of instructions at once in a pipeline method has become common.

When testing the pipeline mechanism of a computer system using such a pipeline method, generally speaking, the computer system's service processor (SVP), which is equipped to maintain and operate the computer system, is tested. central processing unit (CPU)
Since then, a method has been adopted to issue a so-called maintenance order and test the pipeline mechanism, but this method has the problem of taking a long time to test, and an effective test method for the pipeline mechanism has been awaited. I'm getting used to it.

[Conventional technology]

FIG. 4 is a diagram illustrating a conventional test method for a pipeline mechanism, in which a shows the hardware configuration and b shows a flowchart of the test procedure.

First, at the beginning of the test on the pipeline mechanism, the central processing unit (hereinafter referred to as CPU)
1 executes the test program on the main memory (MS) 3 and executes the test program on the main memory (MS) 3,
issue a maintenance order for 2) and
Start the test program provided on the second side. (See step 20) In SVP2, by executing the test program (changing the hardware mechanism of CPU1), the pipeline mechanism in CPU1 is initialized (the pipeline is in a state where nothing is input). ) is done,
Set the instruction under test to CPU1, set the operation mode of CPU1 to 1-step mode, for example,
The CPU 1 is caused to execute the instruction under test for one clock. (See steps 21 and 22).

Thereafter, in order to see the result of the CPU 1 executing the instruction under test in the one-step mode, a scanout is performed and the test result is confirmed.

The above test is performed, for example, on a plurality of instructions under test, and the fault location in the pipeline mechanism is identified based on the test results. (See steps 23 and 24.) When the series of tests for the pipeline mechanism is completed, the operation mode of the CPU 1 is set to normal mode (restoration of the hardware mechanism of the CPU 1), and control is returned to the CPU 1 to perform a series of diagnostics. Processing ends. (See step 25) [Problem to be solved by the invention] Therefore, in the conventional method, it is necessary to issue a maintenance command on the CPU 1 side every time a test is performed, and the configuration of the test program on the CPU 1 side becomes complicated. A problem arose.

Also, on the SVP2 side, it is necessary to provide a test program that is activated by the maintenance command issued by the CPU1, and in order to test the pipeline mechanism of the CPU1, it is necessary to install a test program on both the CPU1 side and the CPU2 side. There was a problem of having to prepare a test program.

In view of the above-mentioned drawbacks of the conventional art, an object of the present invention is to provide a method for efficiently confirming the normality of a pipeline mechanism in a CPU by testing the pipeline mechanism with a step-by-step sequence of test instructions. That is.

[Means for solving problems]

FIG. 1 is a diagram explaining the concept of the present invention.

In the present invention, in order to test the pipeline mechanism of the CPU 2, a test instruction sequence containing only general suspect instructions and a test instruction sequence consisting of alternate combinations of serialized instructions and a plurality of suspect instructions are stored in the main memory. Prepared on the device (MS) and stored in the main storage device (MS)
The processing results obtained when the test instruction sequence read out from .

[Effect]

That is, according to the present invention, in an information processing apparatus that is processed in a pipelined manner and is equipped with a serialization instruction processing mechanism, a test instruction sequence of only general instructions,
A processing result obtained by preparing a test instruction sequence containing serialized instructions on the main memory (MS) and inputting the test instruction sequence containing only general instructions read from the main memory (MS) into the pipeline. By comparing the processing results obtained by inputting a test instruction sequence ~ in which serialization instructions and general instructions are arranged alternately into the same pipeline, the failure point of the pipeline mechanism can be identified. Therefore, the pipeline can be tested stage by stage by selecting (1) step-by-step test instruction sequences. (2) There is no need to use maintenance instructions on the CPU side, which simplifies the configuration of test programs. (3) Since there is no need to use SVP with slow processing speed, there are effects such as shortening test time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Fig. 2 is a diagram showing an embodiment of the present invention, in which a schematically shows the block configuration, b shows the operation in a flowchart, and Fig. 3 shows the configuration of the pipeline mechanism. FIG.

The pipeline mechanism 1a in this embodiment has a five-stage configuration from stage 1 to stage 5, as shown in FIG.

Furthermore, when a serialized instruction is input into a pipeline and recognized as a serialized instruction in the first stage, it outputs the instructions that have already been input into the pipeline and executes the next instruction. The instructions entering the pipeline are suppressed, and when the above-mentioned ejection is completed, the next instruction is allowed to enter the pipeline mechanism, and from then on, the instruction is executed like a general instruction (however, a no-operation instruction). It functions to pass through a pipeline mechanism.

Hereinafter, a method for testing a pipeline mechanism according to the present invention will be explained with reference to FIGS. 2 and 3 while referring to FIG. First, in FIG. 2, Step 10: As mentioned above, since the pipeline 1a shown in this embodiment has a five-stage configuration, for example, five
A test instruction string consisting of instructions (instruction 1 to instruction 5) is created on the main memory device (MS) 3.

If the target is a pipeline mechanism with n stages, n instructions are required.

Step 11: Next, operand data is set in registers, memory, etc. in the pipeline mechanism 1a shown in FIG. 3 to create an environment in which the above instruction sequence can be executed.

Steps 12 and 13: The test instruction string created in step 10, which does not include serialized instructions, is read from the main memory (MS) 3, sequentially input to the pipeline 1a and executed, and the execution results (registers, memory ) is collected and used as the expected value.

Step 14: Set a serialization instruction between each instruction in the test instruction sequence that does not include the serialization instruction created in step 10, and store the test instruction sequence group containing the serialization instructions shown in FIG. (MS)
3 Create on top.

In the test instruction sequence group ~ in FIG. 1, is a test instruction sequence that is passed through the pipeline mechanism 1a of FIGS. 2 and 3 for one instruction (instruction 1, . . . , instruction 5).

is a test instruction sequence for simultaneously passing two instructions (instructions 1 and 2, or instructions 3 and 4, etc.) through the pipeline mechanism 1a.

Similarly, the test instruction sequences indicated by ~ are test instruction sequences that cause the pipeline mechanism 1a to pass only the instructions sandwiched between serialized instructions.

As described above, the test instruction sequences used in the present invention are characterized in that the number of instructions input to the pipeline mechanism 1a at one time is graded in each sequence.

Step 15: As set in step 11, operand data is set in the registers, memory, etc. in the pipeline mechanism 1a to create an environment in which the above instruction sequence can be executed.

Steps 16, 17, 18: Read the test instruction sequence~ created in step 14 from the main memory (MS) 3, and execute the test instructions in the pipeline 1a.
Collect the execution results (registers, memory, etc.) of the serialized instructions, and compare the execution results (expected values) that do not include the serialized instructions collected in step 13 and the execution results that do not include the serialized instructions. Compare the results with the execution results.

This process is carried out by the test instruction sequence shown in Figure 1.
and check if it completed successfully.

If an error is detected, the pipeline mechanism 1a
You can know at which stage the error occurred.

For example, in the pipeline mechanism 1a of FIG. 3, if there is a failure in stage 3, the test instructions in FIG. Since the number of instructions is configured to be different, depending on the position of the failure stage and the combination of the above instruction sequences, for example, there are instruction sequences that will cause an error due to a register conflict, etc., and instruction sequences that will not cause an error. will exist.

Therefore, a large number of test instruction sequences such as ~ in Fig. 1 are provided corresponding to each stage of the pipeline 1a to be tested, and each is passed through the pipeline mechanism to determine which instruction sequence causes an error. By analyzing the failure stage, the failure stage can be detected.

That is, in the present invention, when a certain stage of the pipeline 1a is a failure, the pipeline 1a
This test method focuses on the fact that an error does not occur when a single instruction is sent to a single instruction, but an error may occur when multiple instruction sequences are sent at once due to the interrelationship of the instructions.

In this way, in the present invention, the calculation result (expected value) when a test instruction sequence that does not include serialized instructions is input into the pipeline mechanism, and the test instruction sequence that is a combination of serialized instructions and the above instruction sequence are calculated. Create a group, change the number of instructions flowing through the pipeline mechanism at once, compare the operation results when inputting them to the pipeline mechanism, and determine which combination causes an error. The feature is that it detects the failure stage of the pipeline mechanism.

〔Effect of the invention〕

As described above in detail, the pipeline device testing method of the present invention is performed in an information processing device that is processed in a pipeline manner and is equipped with a serialization instruction processing mechanism, and uses a test instruction sequence of only general instructions.
A processing result obtained by preparing a test instruction sequence containing serialized instructions on the main memory (MS) and inputting the test instruction sequence containing only general instructions read from the main memory (MS) into the pipeline. By comparing the processing results obtained by inputting a test instruction sequence ~ in which serialization instructions and general instructions are arranged alternately into the same pipeline, the failure point of the pipeline mechanism can be identified. Therefore, the pipeline can be tested stage by stage by selecting (1) step-by-step test instruction sequences. (2) There is no need to use maintenance instructions on the CPU side, which simplifies the configuration of test programs. (3) Since there is no need to use SVP with slow processing speed, there are effects such as shortening test time.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the concept of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the configuration of a pipeline mechanism, and Fig. 4 is a diagram showing a conventional pipeline mechanism. It is a figure explaining the test method of a mechanism. In the drawing, 1 is a central processing unit (CPU);
a indicates a pipeline or a pipeline mechanism; 2 indicates a service processor (SVP); 3 indicates a main memory (MS); 10 to 18 and 20 to 25 indicate processing steps; and .about. a test instruction sequence.

Claims (1)

[Scope of Claims] 1. In an information processing device that is processed in a pipeline system and is equipped with a serialization instruction processing mechanism, a test instruction sequence of only general instructions and a test that mixes the general instructions and serialization instructions. Instruction sequence~
are set on the main memory (MS) 3, and the test instruction sequence read from the main memory (MS) 3 is sequentially executed in the pipeline 1a.
and the processing results of the test instruction sequence containing only the general instructions and the test instruction sequence including serialization instructions ~
The pipeline mechanism is characterized in that, after the pipeline operation is temporarily stopped by the serialization instruction, the processing results obtained when the plurality of general instructions are executed are compared. Test method.