JPH04316131A - Fault identifying method - Google Patents

Abstract

PURPOSE:To specify such a fault that the process corresponding to a specific input sequence is omitted or an erroneous output response is returned and, at the same time, to identify a fault even when no sufficient data are available by deleting an hypothesis which is contradictory to the behavior of an automatic machine. CONSTITUTION:A binary adder 108 accepts an input sequence through a data input device 109 and presents a result through a data output device 110 and, when the adder 108 presents the result, writes its internal state in an internal state storage device 111. A data collecting device 103 collects the input sequence, internal state, and output response of the adder 108 as data. A hypothesis management device 104 requests a hypothesis preparing device 105 to prepare the hypothesis 106 of a fault or deletes the hypothesis of a fault which is contradictory to the collected data. The device 105 prepares the hypothesis of the fault based on the design information 101 in response to the request from the device 104 and an input sequence preparing device 107 prepares the input sequence which is the most effective for selecting the hypotheses based on the hypothesis of the fault.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for identifying faults in automatic machines, and more particularly to a method for identifying faults using design information.

0002

[Background Art] Conventionally, as a method for identifying faults in automatic machines, for example, a direct sum machine is constructed from models of a normal automatic machine and a malfunctioning automatic machine, and faults are identified from an input series and an output response. The method of
It is described in. In this method, a new state transition table is obtained by vertically arranging the state transition tables of sequential machines that have a common set of inputs with common columns corresponding to the inputs, and the sequential machine represented by this new state transition table is directly created. It is called a Japanese machine.

0003

[Problems to be Solved by the Invention] However, the above-mentioned prior art only deals with failures that cause a transition to an incorrect internal state for a specific input series, and the process corresponding to the specific input series is missing. It does not address failures that cause errors or produce incorrect output responses. Further, the above-mentioned conventional technology assumes that the automatic machine accepts all input sequences, and does not mention a failure in which the process is interrupted and stopped because it cannot accept a certain input sequence. In computer systems, even if an abnormality occurs in the system, it is often possible to obtain the internal state, but in many cases, the output cannot be obtained. Considering the above-mentioned circumstances, the above-mentioned conventional technology has many problems when used as a fault identification method in a computer system. The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology, such as missing processing corresponding to a specific input series or incorrect output response. The purpose of this invention is to provide a fault identification method that presents the following problems. Another object of the present invention is to provide a fault identification method when an automatic machine interrupts processing and stops.

0004

[Means for Solving the Problems] The above object of the present invention is to present a specific output response based on its own internal state when a specific input sequence is given, and to In a fault identification method for an automatic machine that changes (transitions), a fault hypothesis is generated based on design information of the automatic machine, and a fault is identified by deleting a hypothesis inconsistent with the behavior of the automatic machine. This is achieved by a characteristic fault identification method.

[0005]

[Operation] In the fault identification method according to the present invention, a fault hypothesis is created based on design information, and the hypothesis is narrowed down based on the output response or internal state when a certain input sequence is given, so This makes it possible to identify faults where processing corresponding to the input sequence is missing, faults that present an incorrect output response, or faults that do not terminate normally, making it possible to identify faults more accurately than before.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment in which the present invention is applied to fault identification in a binary adder 108. This binary adder functions as shown in design information 101. In the design information, the input sequence and output response are expressed in the format of "input sequence/output response", and the transition of the internal state is indicated by the direction of an arrow. The state indicated by the double circle is the final internal state that the binary adder settles into if it operates normally. The initial state is always "q0". When this binary adder operates normally, it outputs "0" for the input sequence "00" and ends normally with an internal state of "q0". Furthermore, for the input series "11,00", "0,1" is output, the internal state is changed in the order of "q0", "q1", "q0", and the process ends normally at "q0". The binary adder receives an input sequence through the data input device 109,
The results are presented through the data output device 110. At that time, the internal state is written to the internal state storage device 111. Note that the internal state storage device 111 retains only the last written state. The failure identification device 102 includes a data collection device 103, a hypothesis management device 104, a hypothesis generation device 105,
It is composed of an input sequence generation device 107. The data collection device 103 collects the input sequence, internal state, and output response of the binary adder as data. Hypothesis management device 1
04 requests the hypothesis generation device 105 to generate a failure hypothesis 106 or deletes a failure hypothesis that is inconsistent with the collected data. The hypothesis generation device 105 generates a failure hypothesis based on the design information 101 in response to a request from the hypothesis management device. The input sequence generation device 107 generates the most effective input sequence for narrowing down the hypotheses based on the failure hypotheses.

FIG. 2 shows a hardware configuration for realizing this embodiment. In the fault identification device shown in this example,
A first CPU 201 that realizes the aforementioned data collection device, a second CPU 202 that realizes a hypothesis management device, a third CPU 203 that realizes a hypothesis generation device, and a fourth CPU 204 that realizes an input sequence generation device. A first storage device 205 that stores information, a second storage device 206 that stores failure hypotheses, an input device 207 that accepts instructions from the user, and a display device 20 that displays the results of failure identification work.
It has 8. The outline of the fault identification method according to this embodiment will be explained below based on the flowchart of FIG. 3. First, it is checked whether there is an input sequence, internal state, and output response, and if so, their data is obtained via the data collection device 103 (block 31). Here, if data is obtained and there is a hypothesis of failure, the hypothesis inconsistent with the data is deleted (block 32). Next, it is checked whether there is a failure hypothesis, and if not, a failure hypothesis is generated based on the design information (block 33). Next, it is determined whether or not to end the process. When it becomes impossible to narrow down the hypotheses, the remaining hypotheses are output as solutions and the process ends (block 34). If the processing does not end, refer to the hypotheses to generate the input sequence most useful for narrowing down those hypotheses (block 3).
5) inputting the generated input sequence into the instrument and testing it (block 36); This completes one cycle, and the process returns to block 31 to collect test results via the data collection device.

Next, the present invention will be explained in detail by showing a specific process for identifying a fault in a binary adder. Figure 4
, FIG. 5, FIG. 12, and FIG. 13 are flowcharts showing details of processing in each block, and FIG. 4 is a hypothesis management method (
Block 32), Figure 5 shows the hypothesis generation method (block 33)
, FIG. 12 corresponds to the end determination method (block 34), and FIG. 13 corresponds to the input sequence generation method (block 35). Note that FIGS. 6 to 11 show examples of hypotheses generated in this embodiment, as described later. If the binary adder fails, first collect data (block 31). In the next hypothesis management (Figure 4), it is first checked whether there are any hypotheses (block 41), and if there are hypotheses, those whose output responses or internal states are inconsistent are deleted (block 42). ~45). If there is a hypothesis but no data, the hypothesis will not be deleted. At the time when this failure identification device is activated, no hypothesis exists, so hypothesis management is not performed. If a hypothesis is deleted, information regarding the output response of that hypothesis is removed from the output response table described below (block 46). The output response table is a result of checking whether each failure hypothesis operates as designed when a certain input series is input. In generating a hypothesis (Fig. 5), first, it is checked whether there is a hypothesis (block 50), and if there is no hypothesis, design information is read (block 51), and a hypothesis is generated by transforming it (block 51). Block 52) and delete hypotheses inconsistent with previously obtained data (block 53) to obtain consistent hypotheses. If there are no more hypotheses as a result of deleting contradictory hypotheses, if there is still room to generate a hypothesis, generate a hypothesis again (block 57). The hypothesis is first created by applying the transformation operator only once,
Thereafter, each time a new hypothesis is generated, the number of times the transformation operator is applied is increased (blocks 54 to 56). As a result, increasingly complex failure hypotheses are generated. Examples of the transformation operator include an operator that causes a specific transition to be omitted from the design information (block 55a), an operator that causes a transition to an incorrect internal state (block 55b), and an operator that causes an incorrect output response to be issued (block 55c). Since no hypothesis exists at the time this failure identification device is activated, a hypothesis is always generated.

FIGS. 6(a-d), FIGS. 7(e-h), FIG. 8(
i to l), Fig. 9 (m to p), Fig. 10 (q to t), and Fig. 11 (u to x) are generated by applying each of the above operators once to the design information of the binary adder. The following hypothesis is shown. Note that only the alphabets in parentheses may be used in later explanations. Figures 6 and 7 are those in which certain transitions are omitted, Figures 8 and 9 are those in which a particular transition is caused to transition to an incorrect internal state, and Figures 10 and 11.
is designed to give an incorrect output response at a specific transition. For example, a in FIG. 6 is a state in which the process of transitioning to "q0" when input sequence "00" is given in state "q0" is omitted, and i in FIG.
0”, when input sequence “00” is given, “q
q in Figure 10 changes the state where the transition should be to ``0'' to ``q1.'' When the input sequence ``00'' is given in the state ``q0,'' the q that should output ``0'' is changed. It is designed to output "1". When generating hypotheses for the first time, these 24 hypotheses are generated, and thereafter, the number of times the operator is applied is increased to gradually generate more complex hypotheses.

In the completion determination (FIG. 12), it is first checked whether there is a hypothesis (block 121), and if there is no hypothesis, it is determined that fault identification has failed (block 122).
, ends the process. If there is a hypothesis, check to see if there is an output response table (block 123). If there is no output response table, processing continues without terminating. on the other hand,
If there is an output response table, and as a result of referencing it, it is predicted that the remaining hypotheses will return incorrect output responses for the same input sequence (block 124), it is determined that further identification is impossible. Then, the remaining hypotheses are displayed (block 125), and the process ends. If not, further narrowing down is continued. In the input sequence generation method (Fig. 13), first, it is checked whether an output response table exists (block 131), and if not, an output response table is created for the existing hypothesis (block 132).
. The output response table is a table that indicates whether a correct output response is obtained when each hypothesis is given an input sequence that can be processed normally if there is no failure. For example, regarding a to h in hypothetical diagrams 6 and 7 above, the output response table for a certain minimum input sequence "00" is:
The result will be as shown in FIG. In Figure 27, a hypothesis that returns a correct output response is marked as "O", and a hypothesis that returns an incorrect output response is marked as "X".
It is shown in As is clear from FIG. 27, the state “q0
”, when input sequence “00” is given, “q0”
Hypothesis a, which lacks the process of transitioning to , does not return a correct output response. Note that, as will be described later, the output response table is created starting from the input sequence of the minimum size and sequentially creating tables for longer input sequences. This output response table is used for termination determination and input sequence generation. Once all input sequences have been used for refinement (block 134), the current table is discarded and a table for the larger input sequence is created (block 135).
). As for the input sequence to be used for testing, the output response table is referred to and the one that has the most hypotheses that return incorrect output responses is selected (block 136). For hypotheses a to x shown in FIGS. 6 to 11, FIG. 28 shows the smallest size input sequences that can be processed normally if there is no failure, that is, "00", "01", and "10". This shows the output response. In this output response table, input series "00", "01", and "10" cover the same number of hypotheses that return incorrect output responses, so any series may be selected. Note that from FIG. 28 onward, the symbol "O" indicating that the output response is correct is not displayed in order to make the diagrams easier to read.

A specific example of fault identification based on the above method will be shown below. The target binary adder has the same fault as the hypothesis shown in FIG. 11x, that is, the state “q
Assume that there is a failure in which when the input sequence "00" is received with "1", "0" is returned instead of "1". Furthermore, it is assumed that no data of the binary adder has been obtained before starting the fault identification work. First, data collection (block 31) is attempted, but no data can be obtained. Next, hypothesis management (block 32)
However, since no hypothesis exists (block 41), a hypothesis is immediately generated (block 33). Since there is no hypothesis (block 50), the design information 101 is read and transformed to generate a hypothesis. Here, since this is the first hypothesis generation, the value of the counter is 1 (block 54), so the transformation operator is applied only once (block 55), and the value of the counter is set to 2 (block 56). Regarding transformation,
First, by dropping certain transitions (block 55a), FIG.
The hypotheses shown from a to h in FIG. 7 are obtained. It is then transformed to transition to the incorrect internal state (block 55b), resulting in the hypotheses shown in Figures 8i to 9p. Finally, it is transformed to output an incorrect value (block 55c) and the hypotheses shown in FIGS. 10q to 11x are obtained. After generating hypotheses in this way, an attempt is made to delete hypotheses that contradict the data obtained so far (block 53), but since there is no data, there are no hypotheses to be deleted. Subsequently, a termination determination is made. Here, we do not finish because there is a hypothesis (block 121) and there is no output response table yet (block 123). Since the process did not end, an input sequence is generated next. Since the output response table does not yet exist, as described above, the output response table for the smallest size input series that can be processed when operating as designed, that is, "00", "01", and "10" (Fig. 28) (block 132). Since each series has not yet been used for narrowing down (block 134), one of these series to be used for inspection is selected. Here, "00" is selected (block 136) and tested (block 36). The above is the first cycle.

In the next second cycle, data is first collected (block 31). Here, it is assumed that as a result of the test, it is found that the binary adder returns a normal output response of "0" and terminates normally at "q0". In the next hypothesis management, since a hypothesis exists (block 41
), check whether there is a record of the output response (block 42). Here we get the output response data, so
Delete contradictory hypotheses a and q (block 44). This is because hypothesis a did not accept the input sequence "00" and was expected to end abnormally. This is also because the hypothesis q was expected to return an abnormal output response of "1". Next, it is determined whether a record of the internal state remains (block 43). Since data "q0" is obtained here as well, contradictory hypothesis i is deleted (block 45). This is because the hypothesis i predicted that the input sequence "00" would end abnormally in the internal state "q1". Subsequently, the hypotheses a, i, and q deleted above are deleted from the output response table (block 46). As a result, the output response table becomes as shown in FIG. The next step is hypothesis generation, but since hypotheses still exist (block 50), an end determination is made. Hypotheses exist (block 121) and an output response table also exists (block 123), but now all hypotheses do not behave incorrectly on the same input sequence (block 124). For example, input series "01"
Hypothesis c returns an incorrect output response, while hypothesis b returns a normal output response. Therefore, the process does not end here. In the generation of the input series, "01" and "10" still remain unused (block 134).
From here, select "01" as the next input series,
Check (block 136). The above is the second cycle.

In the next third cycle, data is first collected (block 31). As a result of the test, here the binary adder returns a normal output response of "1",
Assume that it can be seen that the process has ended normally with "q0". In the next hypothesis management, since a hypothesis exists (block 41)
, check if there is a record of the output response (block 4
2). Here, since output response data is obtained, contradictory hypotheses c and s are deleted (block 44). Hypothesis c
This is because it was expected that the input sequence "01" would not be accepted and the program would terminate abnormally. This is also because the hypothesis s was predicted to return an abnormal output response of "0". Next, it is determined whether a record of the internal state remains (block 43). Since data "q0" is obtained here as well, contradictory hypothesis k is deleted (block 45). This is because the hypothesis k predicted that the input sequence "01" would end abnormally in the internal state "q1". Subsequently, the deleted hypotheses c, k, and s are deleted from the output response table (block 46). As a result, the output response table becomes as shown in FIG. The next step is hypothesis generation, but since hypotheses still exist (block 50), an end determination is made. The hypothesis exists (
Block 121), there is also an output response table (block 123), but here we do not terminate the process since all hypotheses do not behave incorrectly for the same input sequence (block 124). In the generation of the input series, since "10" remains unused (block 134), "10" is selected as the next input series and examined (block 136). This is the third cycle.

In the next fourth cycle, data is first collected (block 31). Here, it is assumed that as a result of the test, it is found that the binary adder returns a normal output response of "1" and terminates normally at "q0". In the next hypothesis management, since a hypothesis exists (block 41
), check whether there is a record of the output response (block 42). Here we get the output response data, so
Delete contradictory hypotheses d and t (block 44). This is because hypothesis d predicted that the input sequence "10" would not be accepted and the process would end abnormally. This is also because the hypothesis t was predicted to return an abnormal output response of "0". next,
Check whether a record of the internal state remains (block 43). Since data "q0" is obtained here as well, contradictory hypothesis l is deleted (block 45). This is because the hypothesis 1 predicts that the input sequence "10" will end abnormally in the internal state "q1". The deleted hypotheses d, l, t are deleted from the table (block 46). As a result, the output table becomes as shown in FIG. The next step is hypothesis generation, but since hypotheses still exist (block 50), an end determination is made. The hypothesis exists (
Block 121), there is also an output response table (block 123), but any hypothesis is expected to return a normal output response. This corresponds to the fact that all hypotheses do not behave "wrongly" for the same input sequence (block 124), so we do not terminate the process here either. In generating the next input sequence, all input sequences have been used so far (block 13
4) Discard this table and select the next smallest input sequence that can be processed if the table operates as designed, i.e. "00,00", "00,01", "00,10"
”, “11,00”, “01,00”, “01,01”
, “01,10”, “10,00”, “10,01” and “10,10” (Fig. 32
) (block 135). Then, the series “1
Since there is a hypothesis that only "1,00" returns an incorrect output response, "11,00" is selected and tested here. This is the fourth cycle.

In the next fifth cycle, data is first collected (block 31). As a result of the test, it is assumed here that the binary adder returns an abnormal output response of "00" and is found to terminate normally at "q0". In the next hypothesis management, since a hypothesis exists (block 41
), check whether there is a record of the output response (block 42). Here we get the output response data, so
Contradictory hypotheses e, f, g, h, j, m, n, o, u, v
, w (block 44). These hypotheses are based on the normal output response “01,00” for the input sequence “11,00”.
This is because I expected it to return `` and exit. Also,
Hypothesis b is deleted because it was predicted that the input series "11,00" would not be accepted. Furthermore, the hypothesis r is “1” which is different from the obtained response “00”.
I expected it to output "1", so I deleted it. Next, it is determined whether a record of the internal state remains (block 43). Since data "q0" is obtained here as well, the contradictory hypothesis p is deleted (block 45). The hypothesis p is based on the input sequence “
This is because it was expected that the process would abnormally end with the internal state "q1" for "11,00". The deleted hypothesis is then removed from the table (block 46). As a result, the output table becomes as shown in FIG. The next step is hypothesis generation, but since hypotheses still exist (block 50), an end determination is made. At this point there are hypotheses and output response tables (blocks 121, 123), and only one hypothesis x
only is left. This corresponds to the case where all hypotheses return incorrect output responses for the same input sequence (block 124), so hypothesis x is output as a solution (
block 125). In the above embodiment, the failure can be correctly identified in the fifth cycle.

Next, as a second specific example, we will show how to identify the fault shown in FIG. 11x, which is the same as the first case, when data regarding the internal state of the binary adder cannot be obtained. The first cycle is the same as the first case. In the second cycle, hypothesis i cannot be deleted because no data regarding the internal state is obtained. Therefore, the output response table obtained in the second cycle is as shown in FIG. Similarly, hypothesis k cannot be deleted in the next third cycle. Therefore, the output response table obtained in the third cycle is as shown in FIG. Similarly, in the next fourth cycle, hypothesis l cannot be deleted. Therefore, the output response table obtained in the fourth cycle is as shown in FIG. At this point, all input sequences have been used (block 134).
, discard this table and create the next table (Figure 37) (block 135). Then, input sequence “11,” which contains more hypotheses that return incorrect output responses.
00” and inspect it. This is the fourth cycle. In the fifth cycle, the input sequence “11,0
0'', hypotheses b, e, f, g, h, j, m, n,
o, r, u, v, and w are inconsistent, and as a result, the output response table shown in FIG. 38 is obtained. Then, the input sequence “00,0
1” and inspect it. In the sixth cycle, hypothesis i is inconsistent with the input series "00,01", and as a result, the output response table shown in FIG. 39 is obtained. Then, the input series "01, 10" containing more hypotheses that return incorrect output responses is selected and tested.

In the seventh cycle, the input series "01
, 10'', hypothesis k is contradictory, and as a result, the output response table shown in FIG. 40 is obtained. Then, input sequence “00,
10" and inspect it. In the 8th cycle,
Since there is no hypothesis that contradicts the input series "00, 10", no hypothesis is deleted. Therefore, the output response table is not updated and remains as shown in FIG. 40. At this point, all hypotheses do not return incorrect output responses for the same input sequence, so select the input sequence "10,00" that contains more hypotheses that return incorrect output responses. and inspect. In the ninth cycle, hypothesis l is inconsistent with the input series "10,00", and as a result, the output response table shown in FIG. 41 is obtained. The remaining hypotheses p and x are both the same input series “11,00”
(block 124). Therefore, the remaining hypothesis is displayed as a solution, and the narrowing down is terminated. That is, the state ``
When receiving "00" in "q1", it should output "1" and transition to "q0", but it was mistakenly output as "q1".
This indicates that either the current state is transitioning to , or that the output is erroneously outputting ``0'' when ``1'' should be output. According to the embodiment described above, even if the internal state of the target device cannot be obtained, the failure can be identified to some extent.

Next, as a third embodiment, a method of generating a failure hypothesis using the experiential knowledge of experts will be described. In this embodiment, the fault identification device 102 is configured as shown in FIG.
As shown in FIG. 2, a knowledge base 140 is added that holds the experiential knowledge of experts. In generating a hypothesis (block 33), the hypothesis generation device 105 uses the knowledge base 14 described above.
It is characterized by generating a hypothesis from scratch using the experiential knowledge of experts. Furthermore, as shown in FIG. 15, the hardware configuration newly includes a third storage device 150 that stores the experiential knowledge of the expert. FIG. 16 is a flowchart showing the hypothesis generation method in this embodiment. In this embodiment, unlike the hypothesis generation method in the first and second embodiments (Fig. 5), a failure hypothesis is generated using the experiential knowledge of experts held in the knowledge base (block 160). The expert's experiential knowledge consists of a condition part and an execution part.The condition part contains "IF" followed by the status of the fault identification work, and the execution part contains "THEN" followed by the hypothesis generation method. Describe. In this embodiment, it is assumed that the following knowledge is held in the knowledge base. (Knowledge 1) IF THEN which has not yet generated a hypothesis
Generate a hypothesis that gives an incorrect output response (Knowledge 2) IF THEN that Knowledge 1 fails Generate a hypothesis that transitions to an incorrect internal state (Knowledge 3) IF THEN that Knowledge 1 and Knowledge 2 fail
Generating a Hypothesis in which a Specific Transition is Missing Here, an example of identifying a fault in this embodiment will be shown. The target binary adder is shown in FIG. 1 as in the first and second embodiments.
The same fault as the hypothesis shown in 1x, that is, the state "q1"
Let us assume that there is a failure in which when the input sequence ``00'' is received, ``0'' is returned instead of ``1''. Further, as in the second embodiment, it is assumed that data regarding the internal state of the binary adder cannot be obtained. In the first cycle, since no hypothesis has been generated yet, knowledge 1 is applied to generate a hypothesis that will produce an incorrect output response. Therefore,
The output response table obtained in the first cycle is as shown in FIG. Below, until the 4th cycle,
Proceeding in the same manner as in the second embodiment, the output response table shown in FIG. 43 is created. In the fifth cycle, the input sequence “1
1,00'', the hypotheses r, u, v, and w contradict each other, and as a result, the output response table shown in FIG. 44 is obtained. At this point, the hypothesis and output response table (block 121,
123), and only one hypothesis x remains. This corresponds to the aforementioned case where all hypotheses return incorrect output responses for the same input sequence (block 124), so hypothesis x is output as a solution (block 125). According to the above embodiment, the failure can be correctly identified in the fifth cycle. Note that compared to the second embodiment shown above, which requires nine cycles, it can be seen that there are cases where the failure can be identified in a shorter time by using the knowledge of experts.

Next, as a fourth embodiment, design information of an automatic machine is held for each module having a specific input/output, and a failure hypothesis is generated for each module, thereby identifying a failure for each module. Show how. Figure 17 shows
Three binary adders (A) 140, (B) 141
, (C) 142 is a module configuration diagram of a compound machine configured by combining. This compound machine has an input device 143
It receives an input series from ~146, and returns an output response from the output device 149. Outputs 147 and 148 of the binary adders (A) and (B) become input sequences to the binary adder (C). The multifunction machine shown in this embodiment receives four-digit input data from the input devices 143 to 146 described above. That is, when "0011" is given as input data, the fourth digit "0" is sent from the input device 143, the third digit "0" is sent from the input device 144, and the second digit "1" is sent from the input device 143. 145, and the first digit “1” is the input device 14.
Accepted from 6. Therefore, when the input sequence "0011,0000" is given, the internal state of the binary adder (A) 140 is "q0→
q0 → q0'', the internal state of the binary adder (B) 141 is ``q0 → q1 → q0'', and the binary adder (
C) The internal state of 142 transitions as "q0→q1→q0" and returns "01" as an output response. If this complex machine is not divided into modules, the entire design information will be the sum of FIGS. 18 to 25. There are the following eight internal states of the compound machine, depending on the combination of the internal states of the binary adders A, B, and C, which are the constituent elements. State S0: A=q0, B=q0, C=q0 State S1: A
=q1, B=q0, C=q0 State S2: A=q1, B=
q1, C=q0 State S3: A=q1, B=q0, C=q
1 state S4: A=q1, B=q1, C=q1 state S5:
A=q0, B=q1, C=q0 state S6: A=q0, B
=q0, C=q1 State S7: A=q0, B=q1, C=
q1

FIG. 18 shows the transition from state S0 to other states, and state S3 is represented by a dotted line.
, S4, and S7 mean that there is no transition from state S0. Hereinafter, FIG. 19 is a diagram of FIG.
0 is from state S2, FIG. 21 is from state S3, FIG.
is a diagram showing the transition from state S4, FIG. 23 from state S5, FIG. 24 from state S6, and FIG. 25 from state S7. As is clear from the above explanation, if a complex machine is treated as a whole, the amount of design information becomes enormous, and the number of hypotheses becomes combinatorially explosive. The number of hypotheses is the multiplier of "the number of possible values for each digit" and "the length of each input series",
It is the product of the "number of states" and the "number of hypothesis generation methods." In this example, the number is 24×8×3=384, meaning that 384 hypotheses must be managed at the same time. Therefore, in this embodiment, design information of an automatic machine is held for each module having a specific input/output, and a failure hypothesis is generated for each module, thereby identifying a failure for each module. In the case of the compound machine shown in this embodiment, there are three binary adders A and B with independent input and output.
, C as one module, and design information is held for each binary adder. The design information of each module is the same as 101 in FIG. By dividing the design information into modules in this way, the number of hypotheses for each module becomes "22 x 2 x 3 = 24", which significantly reduces the number of hypotheses. FIG. 26 is a flowchart showing an overview of this embodiment. As an example, a fault identification method when binary adder B is faulty will be shown. First, it is determined whether there are any modules that have not yet been examined (block 260). Since binary adders A, B, and C have not yet been examined here, first read the design information of binary adder A (block 261) and use the method described in the first or third embodiment. , performs fault identification operations (block 262). Here, since binary adder A is not faulty, the fault cannot be identified. If it cannot be identified, check to see if other modules are faulty (block 263). Here, we will introduce binary adder B as a module that has not yet been investigated.
, C remain (block 260), then the design information of binary adder B is read (block 26).
1) Perform fault identification work (block 262). Since binary adder B is faulty, the fault is successfully identified and the process ends. Note that if a fault cannot be identified even after checking all modules, a message indicating that fault identification has failed is displayed (block 264) and the process ends. According to the above embodiment, by dividing the design information into modules in this way, the number of hypotheses for each module is significantly reduced, and failures can be identified in a shorter time. It should be noted that each of the above-mentioned embodiments is an example of the present invention, and it goes without saying that the present invention should not be limited to these.

[0021]

[Effects of the Invention] According to the present invention, a failure hypothesis is created based on design information and narrowed down based on the output response or internal state when a certain input sequence is given, so it is possible to respond to a specific input sequence. Faults that are missing processing, provide incorrect output responses, or do not terminate normally can be identified. Furthermore, since it is possible to determine a state in which the failure cannot be narrowed down using the output response table, a hypothesis narrowed down as much as possible can be obtained even if sufficient data on the malfunctioning device cannot be obtained. Note that when generating a hypothesis, the number of times the transformation operator is applied is gradually increased, so the hypothesis can be verified little by little. This reduces the amount of memory required at one time. Also,
By utilizing the experiential knowledge of experts, failures can be efficiently identified without generating useless hypotheses. In addition, by gradually increasing the length of the input sequence used for testing, starting from the minimum length, we can reduce the calculation time required to select the input sequence that is most useful for narrowing down the selection, and the calculation time required for testing. can be shortened as much as possible. Furthermore, when selecting the input series mentioned above,
By selecting the hypothesis that returns the most incorrect output responses, it is possible to narrow down the hypotheses in as few times as possible. Furthermore, by handling design information separately for each module, it is possible to prevent combinatorial explosion in the number of hypotheses.

[0022]

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a failure identification device showing an embodiment of the present invention.

FIG. 2 is a hardware configuration diagram of a failure identification device according to an embodiment.

FIG. 3 is a flowchart showing an overview of a fault identification method according to the embodiment.

FIG. 4 is a flowchart showing in detail a hypothesis management method in the failure identification method of the embodiment.

FIG. 5 is a flowchart showing in detail a hypothesis generation method in the fault identification method of the embodiment.

FIG. 6 is a diagram showing an example of a failure hypothesis generated by a hypothesis generation method in the failure identification method of the embodiment.

FIG. 7 is a diagram showing an example of a failure hypothesis generated by a hypothesis generation method in the failure identification method of the embodiment.

FIG. 8 is a diagram showing an example of a fault hypothesis generated by a hypothesis generation method in the fault identification method of the embodiment.

FIG. 9 is a diagram showing an example of a fault hypothesis generated by the hypothesis generation method in the fault identification method of the embodiment.

FIG. 10 is a diagram showing an example of a fault hypothesis generated by the hypothesis generation method in the fault identification method of the embodiment.

FIG. 11 is a diagram showing an example of a fault hypothesis generated by a hypothesis generation method in the fault identification method of the embodiment.

FIG. 12 is a flowchart showing in detail a termination determination method in the failure identification method of the embodiment.

FIG. 13 is a flowchart showing in detail an input sequence generation method in the fault identification method of the embodiment.

FIG. 14 is a configuration diagram of a fault identification device showing another embodiment of the present invention.

FIG. 15 is a hardware configuration diagram of the failure identification device of the embodiment shown in FIG. 14;

FIG. 16 is a flowchart showing in detail a hypothesis generation method in the fault identification method of the embodiment.

FIG. 17 is a module configuration diagram of the compound machine of the embodiment.

FIG. 18 is a diagram illustrating an example of design information of a compound machine according to an embodiment.

FIG. 19 is a diagram illustrating an example of design information of a compound machine according to an embodiment.

FIG. 20 is a diagram illustrating an example of design information of the compound machine of the embodiment.

FIG. 21 is a diagram illustrating an example of design information of a compound machine according to an embodiment.

FIG. 22 is a diagram illustrating an example of design information of the compound machine of the embodiment.

FIG. 23 is a diagram illustrating an example of design information of the compound machine according to the embodiment.

FIG. 24 is a diagram illustrating an example of design information of the compound machine according to the embodiment.

FIG. 25 is a diagram illustrating an example of design information of the compound machine according to the embodiment.

FIG. 26 is a flowchart showing an overview of a fault identification method according to the embodiment.

FIG. 27 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 28 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 29 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 30 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 31 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 32 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 33 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 34 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 35 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 36 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 37 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 38 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 39 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 40 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 41 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 42 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 43 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

FIG. 44 is a diagram showing an example of an output response table in the fault identification method of the embodiment.

[Explanation of symbols]

101: Design information, 102: Fault identification device, 103: Data collection device, 104: Hypothesis management device, 105: Hypothesis generation device, 106: Failure hypothesis, 107: Input sequence generation device, 108: Binary adder, 109: Data input device, 110: Data output device, 111: Internal state storage device, 140: Knowledge base.

Claims (11)

[Claims] 1. Presenting a specific output response based on its own internal state when given a specific input sequence;
Further, in a fault identification method for an automatic machine that changes (transitions) an internal state to a specific state, a failure hypothesis is generated based on design information of the automatic machine, and a hypothesis that is inconsistent with the behavior of the automatic machine is deleted. A fault identification method characterized by identifying faults by 2. The failure hypothesis is generated by deforming the design information such that a specific transition is omitted, a transition is made to an incorrect internal state, or an incorrect output response is issued. The fault identification method according to claim 1, wherein: Claim 3: The hypothesis generation method includes one transformation operation.
3. The fault identification method according to claim 2, wherein a complex hypothesis is generated from a simple hypothesis by starting with only one application and sequentially increasing the number of applications. 4. The determination of whether or not there is a contradiction in the hypotheses is performed by checking whether or not the automatic machine completes normally when given a specific input sequence, and the hypotheses are narrowed down based on the result of this determination. The fault identification method according to claim 1, wherein: [Claim 5] A claim characterized in that the determination of whether or not there is a contradiction between the hypotheses is performed by examining the internal state when a specific input sequence is given to the automatic machine, and the hypotheses are narrowed down based on the result of this determination. Fault identification method according to item 1. [Claim 6] A claim characterized in that the determination of whether or not there is a contradiction between the hypotheses is performed by examining an output response when a specific input sequence is given to an automatic machine, and the hypotheses are narrowed down based on the determination result. Fault identification method according to item 1. 7. The input sequence to be applied to the automatic machine is generated in order of length from among input sequences that would normally operate if there is no failure.
6. The fault identification method according to any one of 6. 8. The input sequence to be applied to the automatic machine is selected from the input sequence that has the highest number of hypotheses that will return an incorrect output response when the input sequence is applied to the automatic machine. The failure identification method described in any of the above. 9. In narrowing down the hypotheses, when no hypothesis can be deleted based on the internal state or output response found by giving a new input sequence, it is determined that the hypotheses cannot be narrowed down any further and the process is terminated. The fault identification method according to any one of claims 4 to 6, characterized in that: 10. The fault identification method according to claim 2, wherein the hypothesis generation method utilizes the experiential knowledge of an expert. 11. The automatic machine design information is held for each module having a specific input/output, and the failure hypothesis is generated for each module, thereby identifying a failure for each module. The fault identification method according to claim 1.