JP3466788B2 - Instruction sequence testing device for information processing equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a test of an information processing apparatus.
The present invention relates to an apparatus , and more particularly to an instruction sequence test apparatus in an information processing apparatus suitable for a test having a large-scale test instruction sequence. Since information processing apparatuses in recent years have a large number of complicated mechanisms, a large-scale instruction test for testing while applying a load to these mechanisms is effective. On the other hand, the early shipment of new products is being called for, and it is required to improve the test efficiency.

In a large-scale instruction sequence test, data comparison is performed at a plurality of checkpoints in an instruction sequence, which means that even in a confirmation test after fault correction, already confirmed checkpoints are executed. It wastes time. In particular, in the test at the time of logic simulation, one program execution time required several tens of minutes to several hours, and it was necessary to eliminate useless time.

[0003]

2. Description of the Related Art In the conventional test method, a plurality of checkpoints are provided in a large-scale test instruction sequence as described above,
At the time of passing the checkpoint, the data at that time, for example, the data of the general-purpose register, the control register, the arithmetic register, the access memory, etc. are compared with the correct answer value. If it is judged as an error in the comparison, the test is terminated, an error message is output, and the tester is notified. Then, after the failure analysis and correction, the instruction sequence is executed again from the beginning to confirm the failure location.

[0004]

As described above, in the conventional test method, when an error is judged when the checkpoint is passed, the test is terminated, the failure analysis is performed, and the instruction sequence is executed again from the beginning. It was For this reason, when an error occurs at the back of a plurality of checkpoints, in the test after the failure correction, the checkpoint that has been confirmed once has to be executed again, resulting in waste. In particular, in the test at the time of logic simulation, as described above, one program execution time required several tens of minutes to several hours, resulting in a lot of wasted time. The present invention was made in order to solve the above-mentioned problems of the prior art, and a first object of the present invention is to reduce the comparison processing time at a checkpoint that has been confirmed once, thereby making it possible to perform a test. It is to shorten the time and improve the test efficiency. A second object of the present invention is to determine the number of checkpoints, check targets, according to the nature of the test instruction sequence, the nature of the test process,
The checkpoint position can be selected to shorten the test time and improve the test efficiency. A third object of the present invention is to make it possible to confirm all tests even if a failure occurs in the test target mechanism without waiting for the correction of the failure, and to improve the test process and the yield.

[0005]

FIG. 1 shows the principle of the present invention. In the figure, 101 is a test instruction sequence, 102 is an access data area accessed by the test instruction sequence, 103 is an input unit for setting a checkpoint address, a checkpoint level, etc., 104 is a comparison / determination unit, and 105 is a checkpoint passage. It is a control means for performing a comparison process between the state of the test object at that time and the correct answer value, and displaying error information and the like when an error occurs. In FIG. 1, the instruction sequence test of the device under test is performed as follows. (1) The operator sets the checkpoint address using the input means 103. The comparison / determination means 104 compares the checkpoint address with the checkpoint address set by the operator when passing through the checkpoint of the test instruction sequence (the SVC instruction is used for the checkpoint in the figure). If the above addresses do not match, the process returns to the test instruction sequence, and the process moves to the address next to the checkpoint address. If they match, the control means 105 compares the correct value with the information indicating the state of the device under test, such as the register information of the device under test and the data in the access data area. Then, when the two match, the process returns to the test instruction sequence, and the process moves to the address next to the checkpoint address. If they do not match, processing such as displaying error information is performed and the processing ends. When an error occurs in the previous test, the error is repaired, the error address at which the error occurs is set, and the test is performed again.

(2) The operator sets the checkpoint level by the input means 103 (sets how many checkpoints to check. For example, when checking every other checkpoint, the checkpoint level is set to 2.
Set to). The comparison / determination means 104 counts the number of checkpoint passages of the test instruction sequence and determines whether the current checkpoint matches the checkpoint level set by the operator. If the number of checkpoint passages does not match the set checkpoint level, the process returns to the test instruction sequence and the process proceeds to the address next to the checkpoint address. If they match, the control means 105 compares the correct value with the information indicating the state of the device under test, such as the register information of the device under test and the data in the access data area. Then, when the two match, the process returns to the test instruction sequence, and the process moves to the address next to the checkpoint address. If they do not match, processing such as displaying error information is performed and the processing ends.

(3) The operator uses the input means 103 to set a check target such as a general-purpose register, a control register, an arithmetic register, or an access data area in the device under test. The comparison / determination means 104
Each time the check point of the test instruction sequence is passed, the check target is the check target set above (general-purpose register, control register, operation register, access data area).
Then, the information is compared with the correct value for the check target set by the operator. If the two match, the test instruction sequence is returned to,
The process moves to the address next to the checkpoint address. If they do not match, processing such as displaying error information is performed and the processing ends.

(4) The operator sets a checkpoint number using the input means 103. Comparison / determination means 10
4 counts the number of checkpoint passages in the test instruction sequence, and determines whether the current checkpoint matches the checkpoint number set by the operator. If the current checkpoint number and the set checkpoint number do not match, the process returns to the test instruction sequence and the process moves to the address next to the checkpoint address. If they match, the control means 105 compares the register information of the device under test, information indicating the state of the device under test, such as data in the access data area, with the correct answer value. Then, when the two match, the process returns to the test instruction sequence, and the process moves to the address next to the checkpoint address. If they do not match, processing such as displaying error information is performed and the processing ends.

( 5 ) Restoration processing means for writing a correct answer value to an error data source such as a register when an error occurs,
The control means 105 is provided with means for stacking error information. Then, when an error occurs, the restoration source restores the error source and the stacking unit stacks the error information. Then, the process returns to the test instruction sequence, and the processing is moved to the address next to the checkpoint address.

According to the inventions of claims 1 to 3 ,
As in (1), (2), (3) and (4) above, the checkpoint address where the error occurred in the previous test, the set checkpoint level, the checkpoint number ,
Register information. Thus the comparison process is performed with the information representing the state of the device under test such as data access data area with correct values, checkpoints once take the confirmation, comparison about the check Target The time can be shortened, and the test time can be greatly shortened compared to the conventional one.

Further, since the number of checkpoints and checkpoint positions can be selected according to the nature of the test instruction sequence and the nature of the test process, the test time can be shortened and the test efficiency can be improved. Further, as in claim 4 , claim 1
By providing the restoration means and the error information stacking means in the inventions of to 3 , even if a failure occurs, all the tests can be performed without waiting for the failure to be repaired. It is possible to improve.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram for explaining a first embodiment of the present invention. This embodiment corresponds to the invention of claim 1 of the present invention. In FIG. 2, 1 is a test instruction sequence and 2 is an access data area accessed by the test instruction sequence. A checkpoint SVC instruction is provided in the test instruction sequence 1, and when the SVC instruction is executed, the process is transferred to the checkpoint control unit 3 by an interrupt and after the comparison process in the checkpoint control unit 3 (error end) If not), the procedure returns to the test instruction sequence, and the instruction next to the SVC instruction is executed. Reference numeral 3 is a checkpoint control unit, and the checkpoint control unit 3 includes a comparison mode determination unit 4, an error address comparison unit 5, a register comparison unit 7, an access area comparison unit 8, an address data holding unit 9, It is composed of a correct answer value storage area 10 in which correct answer values such as register information are stored, and an error control unit 11. 12 is an HMI control unit (HM
I: human interface), the operator inputs the address of the error check point from the HMI control unit 12, and the address data is stored in the address data holding unit 9. In the first test, the address data is set to the initial value (0xFFFFFFFF). If an error occurs in the first test, the error is repaired, the address data is set to the address where the error occurred, and the test is performed again.

Next, the operation of this embodiment will be described. When an SVC instruction comes while the test instruction sequence 1 is being executed, the processing is moved to the checkpoint control unit 3. The checkpoint control unit 3 first checks the address data stored in the address data holding unit 9 in the comparison mode determination unit 4. Then, the address data has an initial value (0xFFFF
FFFF), the processing is moved to the register comparing section 7, and when the address data is other than the initial value, the processing is moved to the error address comparing section 5. The error address comparison unit 5 compares the address of the checkpoint stored in the address data holding unit 9 with the address of the currently executed checkpoint, and if they match, the address data holding unit 9 stores the initial value. (0xFFFF
FFFF) is stored and the process is transferred to the register comparison unit 7.
If they do not match, the test instruction sequence 1 is returned to and the next instruction is executed. The register comparison unit 7 compares the register information of the general-purpose register, the control register, the arithmetic register, etc. at the check point with the correct answer value stored in the correct answer value storage area 10. Then, if the register information matches the correct answer value, the processing is moved to the access area comparison unit 8.
If they do not match, the process is moved to the error control unit 11.

The access area comparison processing section 8 compares the contents of the access data area 2 accessed by the test instruction sequence 1 with the correct answer value stored in the correct answer value storage area 10. If the access area matches the correct answer value, the next instruction of the test instruction sequence 1 is returned. If the access areas do not match, the error control unit 11
Transfer processing to. The error control unit 11 displays the error information and the address of the error check point, and ends the process. That is, in the first test, the initial value (0xFFFFFFFF) is set in the address data holding unit 9, and the comparison process is performed by the register comparison unit 7 and the address area comparison unit 8 for each checkpoint. If an error occurs in the first test, the error is repaired and then the HMI control unit 1
From 2, the error address in which the above error has occurred is set in the address data holding unit 11 and the test is performed again.

During the execution of the test, the error address comparison unit 5 of the checkpoint control unit 3 compares the checkpoint address with the error address. If the checkpoint address does not match the error address, the register The comparison and access area comparison processing is not performed, and the processing is moved to the next instruction of the test instruction sequence 1. Then, when the address of the checkpoint matches the error address set in the address data holding unit 9, the process is moved to the register comparing unit 7 and the access area comparing unit 8 and the comparison process is performed. On the other hand, when the address of the check point matches the error address, the initial value (0xFFFFFFFF) is stored in the address data holding unit 9 as described above.
Is stored, so when the error is repaired and no error occurs in the comparison process, the process moves to the next instruction in the test instruction sequence 1, and thereafter, for each checkpoint,
Comparison processing is performed in the register comparison unit 7 and the access area comparison unit 8. When an error occurs again, the error is repaired as described above, and then the HMI control unit 12
The error address in which the above error has occurred is set in the address data holding unit 9 and the test is performed again. As mentioned above,
In this embodiment, an error address is set in the address data holding unit 9 and the comparison process is not performed until the address of the checkpoint matches the error address. Therefore, the checkpoint once confirmed The comparison process is not performed, and the comparison process can be performed only for the unconfirmed check points, and the test time can be shortened and the test efficiency can be improved.

FIG. 3 is a diagram for explaining the second embodiment of the present invention. The present embodiment corresponds to the invention of claim 2 of the present invention. In FIG. 3, 1 is a test instruction sequence and 2 is an access data area. As in the first embodiment, a SVC instruction for checkpoint is provided in the test instruction sequence 1, and SV
When the C instruction is executed, the processing is moved to the checkpoint control unit 3, after the comparison processing in the checkpoint control unit (when it is not an error end), the process returns to the test instruction sequence, and the instruction next to the SVC instruction is executed. It Reference numeral 3 is a checkpoint control unit, and the checkpoint control unit 3 includes a checkpoint level determination unit 21, a checkpoint counter 22, and a checkpoint level holding unit 2.
3, a register comparison unit 7, an access area comparison unit 8, a correct value storage area 10, and an error control unit 11.
Reference numeral 12 denotes an HMI control unit, and an operator inputs a checkpoint level from the HMI control unit 12 (inputs how often to perform checkpoint comparison processing), and the checkpoint level is a checkpoint level holding unit. 23. For example, when performing register comparison processing and access area comparison processing for even-numbered checkpoints, the operator inputs “2” from the HMI control unit 12 to the checkpoint / level holding unit 23. In addition, the checkpoint level holding unit 23,
1 is set as the initial value.

Next, the operation of this embodiment will be described. When an SVC instruction comes while the test instruction sequence 1 is being executed, the processing is moved to the checkpoint control unit 3. In the checkpoint determination unit 21 of the checkpoint control unit 3, first, "1" is added to the checkpoint counter 22 (initial value is 0), the value of the checkpoint counter 22 is read, and the read checkpoint The value of the counter 22 is divided by the value stored in the checkpoint level holding unit 23. Then, if the remainder is 0, it is determined that the checkpoint is a target checkpoint for register comparison and access area comparison, and the processing is transferred to the register comparison unit 7 and the access area comparison unit 8. If the remainder is other than 0, the test instruction sequence 1 is returned to and the next instruction is executed. Similar to the first embodiment, the register comparison unit 7 compares the register information of the general-purpose register, the control register, the arithmetic register, etc. at the checkpoint with the correct answer value stored in the correct answer value storage area 10. Then, if the register information matches the correct answer value, the processing is moved to the access area comparison unit 8. If they do not match, the process is moved to the error control unit 11.

The access area comparison processing section 8 compares the contents of the access data area 2 accessed by the test instruction sequence 1 with the correct answer value stored in the correct answer value storage area 10. If the access area matches the correct answer value, the next instruction of the test instruction sequence 1 is returned. If the access areas do not match, the error control unit 11
Transfer processing to. The error control unit 11 displays error information and ends the process. As described above, in the present embodiment, the checkpoint level is set in the checkpoint level holding unit 23, and the register comparison and the access area comparison processing are performed only at the corresponding checkpoints. The comparison processing can be performed only at the check points, and the test time can be shortened and the test efficiency can be improved.

FIG. 4 is a diagram for explaining the third embodiment of the present invention. In FIG. 4, 1 is a test instruction sequence and 2 is an access data area. As in the first and second embodiments, a SVC instruction for checkpoint is provided in the test instruction sequence 1 and the SVC instruction is executed. Then, the process is transferred to the checkpoint control unit 3. 3 is a checkpoint control unit, and the checkpoint control unit 3 includes a comparison mode holding unit 24, a register comparison unit 7, an access area comparison unit 8,
The correct value storage area 10 and the error control unit 11 are included. The register comparison unit 7 includes a general-purpose register comparison mode determination unit 71, a general-purpose register comparison processing unit 72, a control register comparison mode determination unit 73, a control register comparison processing unit 74, an arithmetic register comparison mode determination unit 75, and an arithmetic register. The access area comparison section 8 includes an access data area comparison mode determination section 81 and an access data area comparison processing section 82.

Reference numeral 12 denotes an HMI control unit. An operator inputs a comparison mode from the HMI control unit 12, and the input comparison mode is stored in the comparison mode holding unit 24. The comparison mode holding unit 24 is composed of, for example, a 4-bit register. In the case of this embodiment, the first bit (hereinafter referred to as bit 1) is a general-purpose register and the second bit (hereinafter referred to as bit 2) is. The control register, the third bit (hereinafter referred to as bit 3) are assigned to the operation register, and the fourth bit (hereinafter referred to as bit 4) is assigned to the access data area comparison mode. If the bit content is 1, compare them.

Next, the operation of this embodiment will be described. When an SVC instruction comes while the test instruction sequence 1 is being executed, the processing is moved to the checkpoint control unit 3. In the register comparison unit 7 of the checkpoint control unit 3, the general-purpose register comparison mode determination unit 71 determines the bit 1 of the register of the comparison mode holding unit 24, and if it is 1, the general-purpose register comparison processing unit 72.
Then, the correct value stored in the correct value storage unit 10 is compared with the contents of the general-purpose register. Similarly, in the control register comparison mode determination unit 73, bit 2 of the register of the comparison mode holding unit 24 is
If bit 2 is 1, the control register comparison processing unit 74 compares the correct value stored in the correct value storage unit 10 with the content of the control register. Similarly, the arithmetic register comparison mode determination unit 75 determines the bit 3 of the register of the comparison mode holding unit 24, and if the bit 3 is 1, the arithmetic register comparison processing unit 76 causes the correct value stored in the correct value storage unit 10. And compare the contents of the operation register. In the access area comparison unit 8, the access / data area comparison mode determination unit 81 determines the bit 4 of the register of the comparison mode holding unit 24. If the bit 4 is 1, the access / data area comparison processing unit 8
In step 2, the correct answer value stored in the correct answer value storage unit 10 is compared with the contents of the access data area.

When all of the bits 1 to 4 of the register of the comparison mode holding unit 24 are 0, the processing is shifted to the test instruction sequence 1 and the next instruction is executed. If the general-purpose register comparison processing unit 72, the control register comparison processing unit 74, the arithmetic register comparison processing unit 76, and the access / data area comparison processing unit 82 compare with the correct answer value, and if they do not match, the process is performed by the error control unit. The process moves to step 11, the error information is displayed, and the process ends. If the answer is correct, the process moves to the test instruction sequence 1 and the next instruction is executed. As described above, in the present embodiment, the comparison mode is set in the comparison mode holding unit 24, and the register comparison processing and the access / data area comparison processing are performed only for the set mode. It is possible to perform comparison processing only on the register and access data area, and it is possible to shorten the test time and improve the test efficiency.

FIG. 5 is a diagram for explaining a fourth embodiment of the present invention. The present embodiment corresponds to the invention of claim 3 of the present invention. In FIG. 5, 1 is a test instruction sequence and 2 is an access data area. As in the above embodiment, the test instruction sequence 1 is provided with an SVC instruction for checkpoint.
When the instruction is executed, the process is transferred to the checkpoint control unit 3. 3 is a checkpoint control unit, and the checkpoint control unit 3 includes a checkpoint number holding unit pointer 31, a designated checkpoint determination unit 32,
It comprises a designated checkpoint number holding unit 33, a checkpoint counter 34 (initial value is 1), a register comparison unit 7, an access area comparison unit 8, a correct value storage area 10, and an error control unit 11. . Reference numeral 12 denotes an HMI control unit. From the HMI control unit 12, the operator inputs a checkpoint number for performing comparison processing, and the designated checkpoint number is the designated checkpoint number holding unit 3
Held at 3.

Next, the operation of this embodiment will be described. When an SVC instruction comes while the test instruction sequence 1 is being executed, the processing is moved to the checkpoint control unit 3. In the designated checkpoint determination unit 31 of the checkpoint control unit 3, first,
By referring to the checkpoint number stored in the designated checkpoint number holding unit pointer 31, the designated checkpoint number is taken out from the designated checkpoint number holding unit 33 and compared with the value of the checkpoint counter 34. If the designated checkpoint number fetched from the designated checkpoint number holding unit 33 and the value of the checkpoint counter 34 match, the process proceeds to the register comparison unit 7. If they do not match, the values of the designated checkpoint number holding unit pointer 31 and the checkpoint counter 34 are incremented by 1, and the test instruction sequence 1
Return to and move processing to the next test instruction.

In the register comparing section 7, as in the above embodiment, the register information of the general-purpose register, the control register, the arithmetic register, etc. at the checkpoint is compared with the correct answer value stored in the correct answer value storage area 10. Then, if the register information matches the correct answer value, the access area comparison unit 8
Transfer processing to. If they do not match, the error control unit 11
Transfer processing to. The access area comparison processing unit 8 compares the contents of the access data area 2 accessed by the test instruction sequence 1 with the correct answer value stored in the correct answer value storage area 10. And
If the access area matches the correct answer value, the value of the checkpoint number holding unit pointer 31 and the value of the checkpoint counter 34 are incremented by one, and the process is moved to the next test instruction in the test instruction sequence 1. If they do not match, the process is transferred to the error control unit 11. The error control unit 11 displays error information and ends the process. As described above, in this embodiment, since the checkpoint number is set in the checkpoint number holding unit 33 and the register comparison and the access area comparison processing are performed only by the corresponding checkpoint, the necessary checkpoints are set. Only the comparison process can be performed, and the test time can be shortened and the test efficiency can be improved.

FIG. 6 is a diagram for explaining the fifth embodiment of the present invention. This embodiment corresponds to the invention of claim 4 of the present invention. In FIG. 6 , 1 is a test instruction sequence and 2 is an access data area. As in the above embodiment, the test instruction sequence 1 is provided with an SVC instruction for checkpoint.
When the instruction is executed, the process is transferred to the checkpoint control unit 3. Reference numeral 3 is a checkpoint control unit, and the checkpoint control unit 3 includes a register comparison unit 7, an access area comparison unit 8, a correct value storage area 10, and an error control unit 1.
The error control unit 11 is provided with a unit 111 for stacking error information and a unit 112 for performing error recovery processing. Reference numeral 55 denotes a means for displaying an error stack, and the error information stacked by the error control unit 11 is displayed on the display means 55 when the processing of the test instruction sequence 1 is completed.

Next, the operation of this embodiment will be described. When an SVC instruction comes while the test instruction sequence 1 is being executed, the processing is moved to the checkpoint control unit 3. Checkpoint control unit 3
In the register comparison unit 7 of the general-purpose register, the control register, the arithmetic register, etc., the correct value storage area 10
Compare with the correct answer value stored in. Then, if they match, the processing is moved to the access area comparison unit 8, and if they do not match, the processing is moved to the error control unit 11. In the access area comparison unit 8, the contents of the access area and the correct value storage area 1
The value is compared with the correct answer value stored in 0, and if they match, the procedure returns to the test instruction sequence 1 to move the processing to the next instruction, and if they do not match, the processing moves to the error control unit 11. The error control unit 11 stacks the error information by the means 111 for stacking the error information, and rewrites the data at the location where the error has occurred to the correct value by the means 112 for recovering the error and performs the processing for the next comparison processing. Transfer. When an error occurs as described above, a test is performed while performing the restoration process. When the test instruction sequence 1 is completed to the end, the stacked error information is displayed by the error stack display unit 55.

This embodiment can be applied to the above-mentioned first to fourth embodiments, and in the case of applying to the first to fourth embodiments, the error control section 11 can detect the above-mentioned error. A means 111 for stacking information and a means 112 for recovering an error are provided, and when the test instruction sequence 1 is completed to the end, the stacked error information may be displayed by the means 55 for displaying an error stack. .
By doing so, the specified checkpoint without error termination test comparison mode,
Can be run to the end. As described above, in the present embodiment, when an error occurs, the test is performed while performing the restoration process, so that even if there is a failure in the test target, it is not necessary to wait for the failure to be corrected. A test can be performed and confirmed, which can contribute to shortening the test process and improving the yield.

[0029]

As described above, in the present invention,
The following effects can be obtained. (1) correct checkpoint address where the error occurred in the previous test, set checkpoint level, the only checkpoint number, register information, and information indicating the state of the device under test such as data access data area since to perform the comparison processing between the value it may be once confirmed is taken, to reduce the comparison processing time for checkpoint like. Therefore, it is possible to test the unconfirmed checkpoint, etc. only, the test time can be greatly shortened compared to the conventional. (2) test instruction sequence personality checkpoint number depending on the nature of the testing process, it is possible to select a checkpoint position 置等, it is possible to improve the test efficiency. (3) By providing error recovery processing means for writing the correct answer value to the error source and error information stacking means,
Even if a failure occurs, the entire test can be performed without waiting for the failure to be repaired, and the test process and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram illustrating a first embodiment of the present invention.

FIG. 3 is a diagram illustrating a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating a fifth embodiment of the present invention.

[Explanation of symbols]

1 Test instruction sequence 2 Access data area 3 Checkpoint control unit 4 Comparison mode determination unit 5 Error address comparison unit 7 Register comparison unit 8 access area comparison section 9 Address data storage 10 Correct value storage area 11 Error control section 12 HMI control unit 21 Checkpoint / level judgment section 22 Checkpoint counter 23 Checkpoint / level holding unit 24 Comparison mode holding unit 31 Checkpoint number holding unit pointer 32 Designated checkpoint judgment section 33 Designated checkpoint number storage 34 Checkpoint counter 71 General-purpose register comparison mode determination unit 72 General-purpose register comparison processing unit 73 Control Register Comparison Mode Judgment Unit 74 Control Register Comparison Processing Unit 75 Operation register comparison mode determination unit 76 Operation register comparison processing unit 81 Access / data area comparison mode determination unit 82 Access / data area comparison processing unit 101 test instruction sequence 102 access data area 103 input means 104 comparison / determination means 105 control means

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinsuke Teranishi 2-15-16 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa FUJITSU COMPUTER TECHNOLOGY INC. (56) Reference JP-A-5-81069 (JP, A) Kaihei 7-28663 (JP, A) JP 7-141218 (JP, A) JP 6-177944 (JP, A) JP 64-3750 (JP, A) JP 64-55653 ( JP, A) JP 2-10442 (JP, A) JP 5-241887 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/22

Claims (4)

(57) [Claims] 1. An instruction sequence test apparatus in an information processing apparatus for executing a test instruction sequence set with a checkpoint to test a device under test, the test instruction sequence having an error in a previous test. Means for inputting the address of the checkpoint, comparison means for comparing the input address of the checkpoint with the address of the current checkpoint, and the device under test at the checkpoint when the comparison results of the comparison means match. The information indicating the state of is compared with the correct answer value, error processing is performed when the information does not match the correct answer value, and when they match, the input checkpoint address is returned to the initial value and the checkpoint of the test instruction string is returned. An instruction sequence test apparatus in an information processing apparatus, comprising: a control unit that shifts processing to the next instruction. 2. An instruction sequence test apparatus in an information processing apparatus for executing a test instruction sequence for which a checkpoint is set and testing a device under test, wherein every few checkpoints of the test instruction sequence. Means for inputting a checkpoint level code that indicates whether to perform checkpoint comparison processing, and a means for determining whether the current checkpoint matches the checkpoint determined by the checkpoint level code, and For the checkpoint determined to match by the determination means, information indicating the state of the device under test is compared with the correct answer value, error processing is performed when the information does not match the correct answer value, and when the information matches, the test instruction string In an information processing apparatus characterized by comprising a control means for shifting the processing to the next instruction of the checkpoint. Instruction sequence test equipment. 3. An instruction sequence test apparatus in an information processing apparatus for executing a test instruction sequence set with check points to test a device under test, the test instruction sequence being a target of comparison processing. Information indicating the state of the device under test for the means for inputting the point number, the means for judging whether or not the current checkpoint matches the above checkpoint number, and the checkpoints judged to match by the above judging means Is compared with a correct answer value, error processing is performed when the information does not match the correct answer value, and when the information is matched, the control means is provided for moving the processing to the instruction next to the check point of the test instruction sequence. Instruction sequence testing device in information processing device. 4. The error recovery processing means for writing the correct value to the data source of the device under test, and the stack for stacking the error information, when the control device does not match the correct value with the information indicating the state of the device under test. An instruction sequence test apparatus in an information processing apparatus according to claim 1, 2 or 3, further comprising a means.