JP3291391B2 - Arithmetic unit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit test apparatus for performing a test process on a plurality of arithmetic units that execute the same arithmetic process, and more particularly, to an accurate test process using small test data. The present invention relates to an arithmetic unit test device.

[0002]

2. Description of the Related Art When performing a logical verification of a vector operation device composed of a plurality of operation units, a plurality of test data based on the method of realizing the operation and the characteristics of operand data are prepared. The test data is executed by the vector operation device, and processing for confirming the operation result and the status after the operation is executed.

[0003] Since this test data is usually a very large data group, a configuration is adopted in which operand elements are arranged without duplication. When such test data in which each operand element occurs only once in a series of test instructions is used, each operand element is executed by only one of the plurality of arithmetic units, and thus a specific arithmetic unit is used. May fail to detect data-dependent faults caused only by certain operand elements of

[0004] Conventionally, test data composed of the same test data for the number of processing units is prepared by expanding the original test data for the number of processing units, and the same test data is stored in each processing unit. By performing the calculation, the same level test is performed for all the arithmetic units.

[0005]

However, according to such a conventional technique, the amount of test data increases proportionally with the increase in the number of arithmetic units. However, there is a problem that a large-capacity memory is required to hold the test data. This is a very serious problem in practical use since a large amount of test data is required even in the case of one arithmetic unit.

Further, according to such a conventional technique, there is a problem that the number of accesses to the magnetic disk device holding the test data increases due to an increase in the amount of test data, and the test time becomes longer.

[0007] The present invention has been made in view of the above circumstances, and a new test method capable of performing accurate test processing using small test data on a plurality of arithmetic units that execute the same arithmetic processing. The purpose of the present invention is to provide an arithmetic unit test device.

[0008]

FIG. 1 and FIG. 2 show the principle configuration of the present invention. In the figure, reference numeral 1 denotes an arithmetic unit, and a plurality of arithmetic units 10-i (i = 1 to 1) executing the same arithmetic processing
An arithmetic unit test apparatus 2 according to the present invention, which includes the function m), executes a test process of the arithmetic unit 10-i.

FIG. 1 shows a computing unit test apparatus 2 whose principle configuration is illustrated.
0, management means 21, replacement means 22, shift means 2
3, setting means 24, input means 25, and moving means 26
, Reverse moving means 27, comparing means 28, specifying means 29
And

The test data string storage area 20 stores the operation unit 1
Manages test data strings given to 0-i. Management means 21
Manages the correct answer value data of the operation result of the test data string stored in the test data string storage area 20 according to the data order of the test data string. The exchange means 22 exchanges the data order of the test data strings stored in the test data string storage area 20.

The shift means 23 stores the test data string storage area 2
The test data sequence is read from 0, and the read test data sequence is cyclically shifted by the set shift amount.
The setting unit 24 sets a shift amount for the shift unit 23. The input unit 25 divides the test data sequence output from the shift unit 23 according to the number of arithmetic units and supplies the test data sequence to each arithmetic unit 10-i in data order.

[0012] The moving means 26 cyclically shifts the correct value data managed by the managing means 21 by the shift amount of the shifting means 23. The reverse moving means 27 cyclically shifts the operation result data output from each of the calculators 10-i in reverse by the shift amount of the shift means 23. The comparing means 28 detects whether each of the computing units 10-i is normal or abnormal according to the comparison process. The specifying means 29 specifies the name of the computing unit in an abnormal state.

On the other hand, a computing unit test apparatus 2 whose principle configuration is shown in FIG. 1 is a test data string storage area 20 / exchange means 22 / shift means 2 described with reference to FIG.
In addition to 3 / setting means 24 / input means 25 / comparing means 28 / specifying means 29, an adjusting means 30 is provided.

The adjusting means 30 adjusts the operation result data output from each of the arithmetic units 10-i so that the data order is prescribed.

[0015]

In the computing unit test apparatus 2 of the present invention whose principle configuration is shown in FIG. 1, when started, the setting means 24 first sets the shift amount "0" to the shift means 23, and sets this value. The shift means 23 receives the test data string storage area 20
The test data string read from the shift means 23 is output to the input means 25 as it is, and the input means 25 divides the test data string output from the shift means 23 in accordance with the number of operation units, and as shown in FIG. This is given to the arithmetic unit 10-i.

When the operation result data is output from each of the computing units 10-i in response to the input of the input means 25, when the moving means 26 is provided, the comparing means 28 Circulates the correct value data by the shift amount of the shift means 23 (in this case, the shift amount "0"), so that the correct value data output from the moving means 26 and the output value from each of the arithmetic units 10-i By comparing the calculated operation result data with the calculated operation result data, it is checked whether or not the operation unit 10-i indicating the abnormality exists.

On the other hand, when the reverse moving means 27 is provided, the comparing means 28 converts the operation result data output from each computing unit 10-i by the shift amount of the shift means 23 when the reverse moving means 27 is provided. (In this case, the cyclic shift is performed in reverse by the shift amount “0”.) By comparing the operation result data output from the reverse moving means 27 with the correct answer value data managed by the management means 21, the abnormal shift is performed. It is checked whether or not there is a computing unit 10-i indicating.

Subsequently, the setting means 24 sets the shift amount "1".
Is set in the shift means 23, and in response to this setting, the shift means 23 cyclically shifts the test data sequence read from the test data sequence storage area 20 by one data to input means 25.
As shown in FIG. 4, the input means 25 divides the test data string output from the shift means 23 according to the number of processing units, and gives the test data sequence to each of the processing units 10-i in the data order.
The comparing unit 28 checks for the presence of the arithmetic unit 10-i indicating an abnormality.

The setting means 24 follows the same processing.
When the number of data n in the test data string is an integral multiple of the number of arithmetic units m each time the inspection process of the comparing means 28 is completed, as shown in FIG. ) Are set in the shift means 23 while being updated one by one, and the inspection processing by the comparing means 28 is executed accordingly.

In this way, by adopting a configuration in which the test data sequence having a single configuration is given to the arithmetic unit 10-i while circulating one by one, for example, when the number of data in the test data sequence Di is six,
To explain with an example in which the number of the arithmetic units 10-i is three,
As shown in FIG. 6, the same test data group can be given to each of the computing units 10-i indicated by and so that the same level test can be performed.

On the other hand, when the number n of data in the test data string is not an integral multiple of the number m of arithmetic units, the shift amount x is set to (m−
The same test data element can be given to each computing unit 10-i by setting the shift means 23 while updating one by one up to the added value of 1) and the surplus number. To perform the same level of testing. For example, when the number of data in the test data sequence Di is five,
For example, as shown in FIG. 7 and FIG. 8, the same test data element may be given to each of the computing units 10-i indicated by. The same level of testing can be performed if possible.

In the computing unit test apparatus 2 of the present invention whose principle configuration is shown in FIG. 2, the shift means 23 circulates and shifts the test data sequence by the set shift amount in the same manner as in FIG. And the input means 25 is the shift means 2
When the test data string output from the third unit is divided according to the number of arithmetic units and input to each arithmetic unit 10-i in data order,
The adjusting unit 30 rearranges the operation result data output from each of the arithmetic units 10-i so that the data order is stipulated, and the comparison unit 28 collects the rearranged operation result data. . For example, the adjusting means 30 rearranges the output operation result data so as to correspond to the data order of the test data sequence in the test data sequence storage area 20, and the comparing means 28 rearranges the rearranged operation result data. Collect.

When the comparison means 28 collects the operation result data for all the set shift amounts, the comparison means 28 compares the collected operation result data with each other to determine the presence of the operation unit 10-i indicating the abnormality. inspect.

As described above, in the arithmetic unit test apparatus 2 of the present invention whose principle configuration is shown in FIG. 2, the arithmetic unit test apparatus of the present invention whose principle configuration is illustrated in FIG. Thus, a test process equivalent to the test process 2 can be performed.

As described above, according to the present invention, accurate test processing can be performed on a plurality of arithmetic units that execute the same arithmetic processing using small test data.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments. FIG. 9 illustrates a system configuration of a computer provided with the present invention.

In the figure, 40 is a scalar operation device, 50 is a vector operation device, and 60 is a main storage device. The scalar operation device 40 includes a scalar operation unit 41, a scalar register 42 serving as a buffer between the main storage device 60, and an instruction execution control unit 43, and stores a scalar instruction described in a program. Execute.

The vector operation device 50 includes a vector register 52 which functions as a buffer between the m vector operation devices 51-i (i = 1 to m), a main storage device 60, and a vector instruction execution control section. 53, when a vector instruction is present in the program, the operands of the vector instruction are divided into a plurality of sets, which are input to separate vector computing units 51-i to execute the instructions in parallel.

The main storage device 60 includes a vector calculator 51-i.
A test program 61 for executing the test processing described above, and a test data sequence 62 having a single configuration composed of a plurality of test data sequences
Then, the test instruction data 63 which is a test instruction of the test data sequence 62 and the accurate value data 64 which is a sequence of operation results of the test data sequence 62 in the data order are developed.

FIG. 10 shows an embodiment of a processing flow executed by the test program 61. Next, the test processing of the present invention will be described in detail according to this processing flow. Here, it is assumed that the number of data in the test data sequence 62 is an integral multiple of the number m of the vector computing units 51-i.

When the test program 61 is started, first, in step 1, "0" is set to a variable x indicating a shift amount. Subsequently, in step 2, the test data sequence 62 is read out and cyclically shifted by the value indicated by the variable x. Subsequently, in step 3, the test data string 62 that has been cyclically shifted is given to each vector calculator 51-i in the data order while being divided according to the number of vector calculators 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected.

Subsequently, at step 4, the collected operation result data is cyclically shifted in the reverse direction by the value indicated by the variable x. Then, in step 5, the correct answer value data 64 is read out,
By comparing the read correct value data 64 with the operation result data subjected to the inverse cyclic shift in correspondence with the data elements, it is checked whether or not each vector operation unit 51-i is normal.
Subsequently, in step 6, the value of the variable x is counted up by one. In the following step 7, it is determined whether or not the value of the variable x has reached "m". When the arrival is determined, the process ends.

As described above, the test program 61
By executing the processing flow of FIG. 10, the test data sequence 62 shown in FIG. 11A is cyclically shifted according to the value of the variable x to be transformed as shown in FIG. 51-i to obtain the operation result data as shown in FIG. 11 (c), which is inversely cyclically shifted according to the value of the variable x to transform as shown in FIG. 11 (d). The vector calculator 51-i is inspected by comparing it with the correct value data shown in FIG.

As described above, the test program 61
According to the processing flow shown in FIG. 10, the vector computing unit 51-i is circulated one by one through the test data sequence 62 having a single configuration.
As shown in FIG. 6, the same level test is performed by giving the same test data group to each vector calculator 51-i, as shown in FIG.

Next, FIGS. 12 to 18 show another embodiment of the processing flow executed by the test program 61. FIG. Next, the test processing of the present invention will be described in detail according to these processing flows.

The processing flow shown in FIG. 12 adds the function of outputting the error statistical data of the vector calculator 51-i to the processing flow of FIG. When the test program 61 is started, in accordance with this processing flow, first, in step 1, the variable x indicating the shift amount is set to "0" in step 1. Subsequently, in step 2, the test data sequence 62 is read out and cyclically shifted by the value indicated by the variable x. Subsequently, in step 3, the test data string 62 that has been cyclically shifted is given to each vector calculator 51-i in the data order while being divided according to the number of vector calculators 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected.

Subsequently, in step 4, the collected operation result data is cyclically shifted in the reverse direction by the value indicated by the variable x. Then, in step 5, the correct answer value data 64 is read out,
By comparing the read correct value data 64 with the operation result data subjected to the inverse cyclic shift, corresponding to the data elements,
It is checked whether there is any mismatch, and if so, the mismatched data element number k is specified. Here, this k is defined as a value starting from “0”.

Subsequently, in step 6, using the specified value of k,

[0039]

(Equation 1)

Accordingly, the number e (e = 1 to e) of the vector computing unit 51-i that has executed the test data having a mismatched result.
m) is detected, and the value of a counter E provided in association with the number e is incremented by one according to the detection result.

For example, if the number n of data in the test data sequence 62 is "6", the number m of vector computing units 51-i is "3",
When the shift amount x is “2”, as shown in FIG. 19A, the vector calculator executes the test data D3 and D6, the vector calculator executes the test data D4 and D1, and the vector Since the arithmetic unit executes the test data D5 and D2, for example, when “k = 0” is specified as shown in FIG. 19B according to the equation (1), the vector arithmetic unit is detected as abnormal. Then, the value of the corresponding counter E is incremented by one, and when "k = 4" is specified, the vector arithmetic unit is detected as abnormal and the value of the corresponding counter E is incremented by one. is there.

Subsequently, in step 7, the value of the variable x is counted up by one. In the following step 8, it is determined whether or not the value of the variable x has reached "m", and it is determined that the variable x has not reached. In some cases, the process returns to step 2 and when it is determined that the error has occurred, the process proceeds to step 9 in which the value of the counter E serving as error statistical data (abnormality of each vector calculator 51-i during execution while cyclically shifting the test data sequence 62) Is displayed), and the process ends.

As described above, the test program 61
By executing the processing flow shown in FIG. 12, while performing the same level test on each vector computing unit 51-i using the test data sequence 62 having a single configuration, the vector computing unit 51
-i outputs error statistical data indicating the number of error occurrences.

On the other hand, the processing flow shown in FIG. 13 executes processing equivalent to the processing flow of FIG. 10 without using the correct answer value data 64. Test program 61
When the program is started in accordance with this processing flow, first, in step 1, "0" is set to a variable x indicating the shift amount. Subsequently, in step 2, the test data sequence 62 is read out and cyclically shifted by the value indicated by the variable x. Subsequently, in step 3, the test data string 62 that has been cyclically shifted is given to each vector calculator 51-i in the data order while being divided according to the number of vector calculators 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected.

Subsequently, in step 4, the collected operation result data is cyclically shifted in the reverse direction by the value indicated by the variable x and stored in a prescribed storage area on the main storage device 60. Subsequently, in step 5, the value of the variable x is counted up by one. In the following step 6, it is determined whether or not the value of the variable x has reached "m". When the arrival is determined, the process proceeds to step 7 where all the operation result data stored in the storage area are compared with each other to check whether or not each vector operation unit 51-i is normal. The process ends.

As described above, the test program 61
By executing the processing flow shown in FIG. 13, the test processing equivalent to the processing flow of FIG. 10 is executed without using the correct answer data 64.

On the other hand, the processing flow shown in FIG. 14 performs a high-accuracy test process by exchanging the arrangement of the data elements in the test data sequence 62. When the test program 61 is started, in accordance with this processing flow, first, in step 1, the variable x indicating the shift amount is set to “0” and the number of times the test data sequence 62 is replaced is set in step 1. "1" is set to the variable y to be displayed. Subsequently, in step 2, the arrangement of the data elements of the test data sequence 62 is changed according to a prescribed algorithm,
In the subsequent step 3, the correct answer value data 64 is read out, and the arrangement of the data elements is changed according to the same method as in step 1.

Subsequently, in step 4, the test data sequence 62 replaced in step 3 is cyclically shifted by the value indicated by the variable x. Then, in step 5, the test data 63 is executed by giving the cyclically shifted test data sequence 62 to each vector computing unit 51-i in the data order while dividing it according to the number of vector computing units 51-i. Then, the calculation result data is collected. Subsequently, at step 6, the collected calculation result data is cyclically shifted in the reverse direction by the value indicated by the variable x.
Subsequently, in step 7, the correct answer value data 64 replaced in step 3 and the operation result data subjected to the inverse cyclic shift are compared in correspondence with the data elements, whereby each of the vector operation units 51-i is compared.
Check whether is normal.

Subsequently, in step 8, the value of the variable x is counted up by one, and in the following step 9, it is determined whether or not the value of the variable x has reached "m", and it is determined that the variable x has not reached. In some cases, the process returns to step 4 and when it is determined that the variable y has been reached, the process proceeds to step 10 in which the value of the variable y is counted up by one. In the following step 11, it is determined whether the value of the variable y has reached "M" Then, when it is determined that the vehicle has not arrived, the process returns to step 2, and when it is determined that the vehicle has arrived, the process ends.

In this way, the test program 61
By executing the processing flow illustrated in FIG. 14, the test elements equivalent to the processing flow of FIG. 10 are executed on each of the replaced test data strings while the arrangement of the data elements of the test data string 62 is changed. Then, a high-precision test process is executed.

On the other hand, the processing flow shown in FIG. 15 executes processing equivalent to the processing flow of FIG. 10 by compressing data. When activated, the test program 61 reads the correct answer data 64 in step 1 and compresses the read correct answer data 64 in accordance with a prescribed data compression method in step 1 when started. . Then, in step 2, "0" is set to a variable x indicating the shift amount. Subsequently, in step 3, the test data sequence 62 is read out and cyclically shifted by the value indicated by the variable x. Subsequently, in step 4, the test data string 62 that is cyclically shifted is given to each vector computing unit 51-i in the data order while being divided according to the number of vector computing units 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected.

Subsequently, at step 5, the collected operation result data is cyclically shifted in the reverse direction by the value indicated by the variable x. Subsequently, in step 6, the inversely shifted operation result data is compressed according to the same data compression method as the data compression method in step 1. Subsequently, in step 7, step 1
By comparing the compressed data of the correct answer value data 64 obtained in the above with the compressed data of the calculation result data obtained in the step 6, it is checked whether or not each vector calculator 51-i is normal.
Subsequently, in step 8, the value of the variable x is counted up by one. In the following step 9, it is determined whether or not the value of the variable x has reached "m". When the arrival is determined, the process ends.

As described above, the test program 61
By executing the processing flow shown in FIG. 15, the processing equivalent to the processing flow of FIG. 10 is executed using the compressed data.

On the other hand, the processing flow shown in FIG. 16 executes processing equivalent to the processing flow of FIG. 13 by compressing data. When the test program 61 is started, in accordance with this processing flow, first, in step 1, the variable x indicating the shift amount is set to “0” in step 1.
Is set. Subsequently, in step 2, the test data sequence 6
2 is read out and cyclically shifted by the value indicated by the variable x.
Subsequently, in step 3, the cyclically shifted test data sequence 6
2 is given to each vector computing unit 51-i in data order while being divided according to the number of vector computing units 51-i, the test instruction data 63 is executed, and the computation result data is collected.

Subsequently, in step 4, the collected operation result data is cyclically shifted in the reverse direction by the value indicated by the variable x. Subsequently, in step 5, the cyclically shifted operation result data is compressed according to a prescribed data compression method, and
0 is stored in the specified storage area. Then, step 6
Then, the value of the variable x is counted up by one, and in the following step 7, it is determined whether or not the value of the variable x has reached "m". When it is determined, the process proceeds to step 8, where the compressed data of the operation result data stored in the storage area are compared with each other to check whether each vector operation unit 51-i is normal and to terminate the processing. I do.

As described above, the test program 61
By executing the processing flow shown in FIG. 16, the processing equivalent to the processing flow of FIG. 13 is executed using the compressed data.

On the other hand, the processing flow shown in FIG. 17 executes processing equivalent to the processing flow of FIG. 14 by compressing data. When the test program 61 is started, in accordance with this processing flow, first, in step 1, the variable x indicating the shift amount is set to “0” in step 1.
Is set, and “1” is set to a variable y indicating the number of replacements of the test data sequence 62. Subsequently, in step 2, the test data sequence 62 according to a prescribed algorithm
Swap the order of the data elements. Then, in step 3, the correct answer data 64 is read out, and the arrangement of the data elements is changed according to the same method as in step 1, and in subsequent step 4, the read out correct answer data 64 is compressed according to a prescribed data compression method. .

Subsequently, in step 5, the test data sequence 62 replaced in step 2 is cyclically shifted by the value indicated by the variable x. Subsequently, in step 6, the test data string 62 subjected to the cyclic shift is given to each vector computing unit 51-i in the data order while being divided according to the number of vector computing units 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected. Subsequently, in step 7, the collected operation result data is cyclically shifted in reverse by the value indicated by the variable x.
Subsequently, in step 8, the operation result data subjected to the inverse cyclic shift is compressed according to the same data compression method as the data compression method in step 4.

Subsequently, in step 9, the compressed data of the correct answer value data 64 obtained in step 4 is compared with the compressed data of the operation result data obtained in step 9, so that each of the vector calculators 51-i operates normally. Check if. Subsequently, in step 10, the value of the variable x is counted up by one. In the following step 11, it is determined whether or not the value of the variable x has reached "m". Returning to step 12, when judging the arrival,
Then, the value of the variable y is incremented by one. In the following step 13, it is determined whether or not the value of the variable y has reached "M". When the arrival is determined, the process ends.

As described above, the test program 61
By executing the processing flow shown in FIG. 17, the processing equivalent to the processing flow of FIG. 14 is executed using the compressed data.

Although the processing flow shown in FIG. 10 and the processing flows shown in FIGS. 12 to 17 disclose a configuration in which the correct answer value data 64 is not cyclically shifted, a configuration in which the correct answer value data 64 is cyclically shifted may be employed. It is.

For example, the processing flow shown in FIG. 18 executes a test processing equivalent to the processing flow of FIG. 10 by cyclically shifting the correct value data. That is, when the test program 61 follows this processing flow,
When activated, first, at step 1, "0" is set to a variable x indicating the shift amount. Subsequently, in step 2, the test data sequence 62 is read out and cyclically shifted by the value indicated by the variable x. Subsequently, in step 3, the test data string 62 that has been cyclically shifted is given to each vector calculator 51-i in the data order while being divided according to the number of vector calculators 51-i, and the test instruction data 63 is executed. Then, the calculation result data is collected.

Subsequently, in step 4, the correct answer data 64
And the read correct value data 64 is cyclically shifted by the value indicated by the variable x. Then, step 5
Then, by comparing the operation result data collected in step 3 with the correct answer data 64 cyclically shifted in step 4 in correspondence with the data elements, it is checked whether or not each vector operation unit 51-i is normal. Subsequently, in step 6, the value of the variable x is counted up by one.
It is determined whether or not the value has reached "m". When it is determined that the value has not reached the value, the process returns to step 2, and when it is determined that the value has reached the value, the process ends.

In this way, the test program 61
By executing the processing flow shown in FIG. 18, processing equivalent to the processing flow of FIG. 10 is executed. The combination with the data compression method disclosed in the embodiment is only an example. For example, in the processing flow illustrated in FIG. 17, when the replacement of the test data string 62 and the data compression are combined, it is checked whether or not each vector calculator 51-i is normal using the correct answer data 64. A configuration in which each vector operation unit 51-i is checked for normality by comparing compressed operation result data without using the correct value data 64, It is also possible to take.

Further, in this embodiment, the configuration is disclosed in which the inspection is executed by comparing the result data with the correct value data as soon as the result data is collected. However, after collecting all the result data, It is also possible to adopt a configuration of comparing with the correct answer value data.

In the embodiment, the number of data in the test data string is assumed to be an integral multiple of the number m of the vector calculators 51-i. However, as shown in FIGS. It is not something that can be done.

[0067]

As described above, according to the present invention,
A plurality of arithmetic units executing the same arithmetic processing can be tested at the same level using test data of the same size as test data required for test processing of a single arithmetic unit.

That is, it is possible to detect a data-dependent fault that occurs only by a specific operand element of a specific arithmetic unit while using test data of a single configuration, thereby improving test accuracy.

Since test data of a single configuration is sufficient, the memory capacity can be reduced and the test time can be shortened accordingly, so that the test efficiency can be improved.

Since the correct answer value data can be collected into one, and it is not necessary to have the correct answer value data,
The time required to create the correct answer value data can be significantly reduced, thereby improving the test development efficiency.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a principle configuration diagram of the present invention.

FIG. 3 is an explanatory diagram of a test data string input process.

FIG. 4 is an explanatory diagram of a test data string input process.

FIG. 5 is an explanatory diagram of a shift process of a test data string.

FIG. 6 is an example of a test data string input process;

FIG. 7 is an example of a test data string input process.

FIG. 8 is an example of input processing of a test data string.

FIG. 9 is an embodiment of the present invention.

FIG. 10 is an example of a processing flow executed by a test program.

11 is an explanatory diagram of a test process of the process flow of FIG.

FIG. 12 is another embodiment of the processing flow executed by the test program.

FIG. 13 is another embodiment of the processing flow executed by the test program.

FIG. 14 is another embodiment of the processing flow executed by the test program.

FIG. 15 is another embodiment of the processing flow executed by the test program.

FIG. 16 is another embodiment of the processing flow executed by the test program.

FIG. 17 is another embodiment of the processing flow executed by the test program.

FIG. 18 is another embodiment of the processing flow executed by the test program.

19 is an explanatory diagram of a test process of the process flow of FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic unit 2 arithmetic unit test unit 10 arithmetic unit 20 test data string storage area 21 management unit 22 replacement unit 23 shift unit 24 setting unit 25 input unit 26 moving unit 27 reverse moving unit 28 comparing unit 29 specifying unit 30 adjusting unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22 G06F 17/16

Claims (8)

(57) [Claims] An arithmetic unit test apparatus for performing a test process on a plurality of arithmetic units that execute the same arithmetic process, wherein a shift means for cyclically shifting a given test data sequence by a set shift amount. And input means (25) for dividing the test data string output from the shift means (23) according to the number of arithmetic units and inputting the data to each arithmetic unit in data order, and responding to the input of the input means (25). Means for comparing the operation result data output from each operation unit with the correct answer value data
(28) setting means for setting the shift amount in the shift means (23) while updating the shift amount one by one to a value specified by the number of arithmetic units
(24) An arithmetic unit test apparatus characterized by comprising: 2. The arithmetic unit test apparatus according to claim 1, wherein the managing means manages the correct value data in accordance with the data order of the test data sequence, and the correct value data managed by the managing means is stored in the managing means. Shift means
Moving means (26) for cyclically shifting by the shift amount of (23), and the comparing means (28) is configured to output the correct answer data output from the moving means (26) and the calculation result output from each arithmetic unit. An arithmetic unit test apparatus characterized in that processing is performed to compare with data. 3. The arithmetic unit test apparatus according to claim 1, wherein the managing unit manages the correct value data in accordance with the data sequence of the test data sequence, and shifts the operation result data output from each arithmetic unit. (2
Reverse movement means (27) that reversely circulates the shift amount by the shift amount of 3)
Comparing means (28) performs processing to compare the correct answer data managed by the managing means (21) with the calculation result data output by the reverse moving means (27). Computing unit test equipment. 4. The arithmetic unit testing apparatus according to claim 1, wherein the comparing means (28) compares the compressed data of the operation result data with the compressed data of the operation result data instead of comparing the operation result data with the correct answer value data. ,
An arithmetic unit test apparatus characterized in that processing is performed so as to compare the correct value data with the compressed data. 5. An arithmetic unit test apparatus for performing a test process on a plurality of arithmetic units that execute the same arithmetic process, wherein a shift means for cyclically shifting a given test data sequence by a set shift amount. And input means (25) for dividing the test data string output from the shift means (23) according to the number of arithmetic units and inputting the data to each arithmetic unit in data order, and responding to the input of the input means (25). Adjusting means (30) for adjusting the operation result data output from each of the arithmetic units so that the data order is stipulated, and updating the shift amount one by one to a value specified by the number of the arithmetic units. Setting means for setting the shift means (23) while performing
(24), a comparison means () for collecting operation result data output from the adjusting means (30) in response to the setting of the setting means (24), and comparing the collected operation result data with each other. 28), comprising: a computing unit test apparatus. 6. The arithmetic unit testing apparatus according to claim 5, wherein the comparing means compares the compressed data of the operation result data with each other instead of comparing the operation result data with each other. A processing unit test apparatus characterized by processing. 7. The arithmetic unit test apparatus according to claim 1, wherein the data order of the test data sequence is changed to shift means (23).
A computing device test apparatus, comprising: a replacement means (22) for giving a command to a computer. 8. The arithmetic unit test apparatus according to claim 1, wherein the number of arithmetic units, the shift amount of the shift means (23), and the number of data in the test data sequence. An arithmetic unit test apparatus comprising: an identification unit (29) for identifying an arithmetic unit in an abnormal state from the mismatched data position information detected by the comparison unit (28).